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rev. 1.0 5/07 copyright ? 2007 by silicon laboratories cp2200/1 cp2200/1 s ingle -c hip e thernet c ontroller ethernet controller integrated ieee 802.3 mac and 10 base-t phy fully compatible with 100/1000 base-t networks full/half duplex with auto-negotiation automatic polarity detection and correction automatic retransmission on collision automatic padding and crc generation supports broadcast and multi-cast mac addressing parallel host interface (30 mbps transfer rate) 8-bit multiplexed or non-multiplexed mode only 11 i/o pins required in multiplexed mode intel ? or motorola ? bus format interrupt on received packets and wake-on-lan 8 kb flash memory 8192 bytes isp non-volatile memory factory pre-programmed unique 48-bit mac address no external eeprom required other features led output drivers (link/activity) dedicated 2 kb ram transmit buffer and 4 kb ram receive fifo buffer power-on reset 5 v tolerant i/o software support royalty-free tcp/ip sta ck with device drivers tcp/ip stack configuration wizard hardware diagnostic software and example code example applications remote sensing and monitoring inventory management voip phone adapters point-of-sale devices network clocks embedded web server remote ethernet-to-uart bridge supply voltage 3.1 to 3.6 v package pb-free 48-pin tqfp (9x9 mm footprint) pb-free 28-pin qf n (5x5 mm footprint) ordering part number cp2200-gq (48-pin) CP2201-gm (28-pin) temperature range: ?40 to +85 c figure 1. example system diagram parallel bus host interface 8 kb flash 4 kb rx fifo 2 kb tx buffer ethernet mac ethernet phy rx+/rx- tx+/tx- clock led control 20 mhz xtal rj-45 act led link led cp2200
cp2200/1 2 rev. 1.0
cp2200/1 rev. 1.0 3 t able of c ontents section page 1. system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. typical connection diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5. pinout and package defini tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 6.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 6.2. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3. interrupt request signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4. clocking options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5. led control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6.6. sending and receiving packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7. internal memory and regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1. random access to ram transm it and receive buffers . . . . . . . . . . . . . . . . . . . . . . 23 7.2. internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 8. interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 9. reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1. power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 9.2. power-fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.3. oscillator-fail reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.4. external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.5. software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 9.6. determining the s ource of the last reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.7. de-selecting interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10. power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1. normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2. link detection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.3. memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.4. shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.5. disabling secondary device func tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11. transmit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 11.2. transmitting a packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.3. overriding transmit configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.4. transmit buffer and autowrite interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.5. transmit status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12. receive interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 12.2. reading a packet using the auto read interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.3. timing and buffer over flow considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.4. initializing the rece ive buffer, filter and hash table . . . . . . . . . . . . . . . . . . . . . . . 59
cp2200/1 4 rev. 1.0 12.5. receive status and control regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.6. advanced receive buffer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.7. receive buffer adv anced status and control re gisters . . . . . . . . . . . . . . . . . . . . .67 13. flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.1. programming the fl ash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.2. reading the flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 13.3. flash access registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 14. media access controller (mac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.1. initializing the mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 14.2. accessing the indirect ma c registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.3. indirect mac register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 15. physical layer (phy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 15.1. auto-negotiation and duplex mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 15.2. auto-negotiation synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 15.3. loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 15.4. link integrity function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 15.5. receiver smart sque lch and automatic polarity correction . . . . . . . . . . . . . . . . . . 89 15.6. transmitter jabber function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 15.7. initializing the physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16. parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 16.1. non-multiplexed intel format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 16.2. multiplexed intel format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 16.3. non-multiplexed motorola format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 16.4. multiplexed motorola fo rmat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
cp2200/1 rev. 1.0 5 1. system overview the cp2200/1 is a single-chip ether net controller containing an integr ated ieee 802.3 ethernet media access controller (mac), 10base-t ph ysical layer (phy), and 8 kb non-volatile flash memory available in a compact 5 x 5 mm qfn-28 package (sometimes called ?mlf? or ?mlp?) and a 48-pin tqfp package. the cp2200/1 can add ethernet connectivity to any microc ontroller or host processor with 11 or more port i/o pins. the 8-bit parallel interface bus supports both intel and motorola bus formats in multiplexed and non-multiplexed mode. the data transfer rate in non-multiplexed mode can exceed 30 mbps. the on-chip flash memory may be used to store user cons tants, web server content, or as general purpose non- volatile memory. the flash is factory preprogrammed wit h a unique 48-bit mac address stored in the last six memory locations. having a unique mac address stored in the cp2200/1 often removes the serialization step from the product manufacturing process of most embedded systems. the cp2200/1 has four power modes with varying levels of functionality that allow the host processor to manage the overall system power consumption. the optional interrupt pin also allows the host to enter a ?sleep? mode and awaken when a packet is received or when the cp2200/1 is plugged into a network. auto-negotiation allows the device to automatically detect the most efficient d uplex mode (half/full duplex) supported by the network. the ethernet development kit (ethernet-dk) bundles a c8051f120 mcu target board, cp2200 ethernet development board ( ab4), the silicon lab oratories ide, all necessary debug hardware, and a tcp/ip configuration wizard. the ethernet development kit incl udes all hardware, software, and examples necessary to design an embedded system using the cp2200. the cp2200 ethernet development board is also compatible with the c8051f020tb and c8051f340tb. individual targ et boards may be purc hased online by visiting www.silabs.com.
cp2200/1 6 rev. 1.0 2. typical connection diagram figure 2 and figure 3 show typical connection diag rams for the 48-pin cp2200 and 28-pin CP2201. figure 2. typical connection diagram (non-multiplexed) cp2200 xtal2 xtal1 20 mhz 10 m 22 pf 22 pf +3vd av+ vdd1 vdd2 0.1 uf 0.1 uf 0.1 uf 10 uf mcu cs a[7:0] a15 a[7:0] d[7:0] d[7:0] 8 8 rd rd int int wr wr muxen moten rst 4.7 k +3vd tx+ tx? txp txn tct rx+ rx? rxp rxn rct 8 8 0.001 uf 0.1 uf 0.1 uf 100 rj-45 1 2 3 4 5 6 7 8 link act act link integrated rj-45 jack gnd agnd dgnd2 dgnd1 optional optional chassis ground 1:2.5 1:1 0.001 uf note: the cp220x should be placed within 1 inch of the transformer for optimal performance.
cp2200/1 rev. 1.0 7 figure 3. typical connection diagram (multiplexed) CP2201 xtal2 xtal1 20 mhz 10 m 22 pf 22 pf +3vd av+ vdd1 vdd2 0.1 uf 0.1 uf 0.1 uf 10 uf mcu cs ad[7:0] ad[7:0] 8 rd rd int int wr wr moten rst 4.7 k +3vd la link/activity integrated rj-45 jack gnd agnd dgnd2 dgnd1 optional chassis ground ale ale tx+ tx? txp txn tct rx+ rx? rxp rxn rct 8 0.001 uf 0.1 uf 0.1 uf 100 rj-45 1 2 3 4 5 6 7 8 1:2.5 1:1 0.001 uf 8 note: the cp220x should be placed within 1 inch of the transformer for optimal performance.
cp2200/1 8 rev. 1.0 3. absolute maximum ratings table 1. absolute maximum ratings parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on any i/o pin or rst with respect to gnd ?0.3 ? 5.8 v voltage on v dd with respect to gnd ?0.3 ? 4.2 v maximum total current through v dd and gnd ? ? 500 ma maximum output current sunk by rst or any i/o pin ? ? 100 ma note: stresses above those listed may cause permanent damage to t he device. this is a stress rating only, and functional operation of the devices at or exceeding the conditions in th e operation listings of this sp ecification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
cp2200/1 rev. 1.0 9 4. electrical characteristics table 2. global dc electrical characteristics v dd = 3.1 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units supply voltage 3.1 3.3 3.6 v supply current in normal mode (transmitting) v dd = 3.3 v ? 75 155 ma supply current in normal mode (no network traffic) v dd =3.3 v ? 60 ? ma supply current with transmitter and receiver disabled (memory mode) v dd =3.3 v ? 47 ? ma supply current in reset v dd = 3.3 v ? 15 ? ma supply current in shutdown mode v dd =3.3 v ? 6.5 ? ma specified operating tem perature range ?40 ? +85 c table 3. digital i/o dc electrical characteristics v dd = 3.1 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units output high voltage (v oh )i oh =?3ma i oh =?10a i oh =?10ma v dd ? 0.7 v dd ? 0.1 ? ? ? v dd ? 0.8 ? ? ? v output low voltage (v ol )i ol =8.5ma i ol =10a i ol =25ma ? ? ? ? ? 1.0 0.6 0.1 ? v input high voltage (v ih )2.0??v input low voltage (v il )??0.8v input leakage current ? 25 50 a
cp2200/1 10 rev. 1.0 5. pinout and p ackage definitions table 4. cp2200/1 pin definitions name pin numbers type description 48-pin 28-pin av+ 5 3 power in 3.1?3.6 v analog power supply voltage input. agnd 4 2 analog ground v dd1 13 8 power in 3.1?3.6 v digital power supply voltage input. dgnd1 14 9 digital ground v dd2 30 19 power in 3.1?3.6 v digital power supply voltage input. dgnd2 31 20 digital ground rst 15 10 d i/o device reset. open-drain output of internal por and v dd monitor. an external source can initiate a system reset by driving this pin low for at least 15 s. link 3* ? d out link led. push-pull output driven high when valid 10base-t link pulses are detected (link good) and driven low when valid 10base-t link pulses are not detected (link fail). act 2* ? d out activity led. push-pull output driven high for 50 ms when any packet is transmitted or received and driven low all other times. la ? 1* d out link or activity led. push-pull output driven high when valid link pulses are detected (link good) and driven low otherwise (link fail). the output is toggled for each packet transmitted or received, then returns to its original state after 50 ms. xtal1 46 28 a in crystal input. this pin is the return for the extern al oscillator driver. this pin can be overdriven by an external cmos clock. xtal2 45* 27* a out crystal output. this pin is the excitation driver for a quartz crystal. tx+ 9 6 a out 10base-t transmit, dif ferential output (positive). tx? 10 7 a out 10base-t transmit, dif ferential outp ut (negative). rx+ 7 5 a in 10base-t receive, dif ferential inpu t (positive). rx? 6 4 a in 10base-t receive, dif ferential inpu t (negative). moten 43 26 d in motorola bus format enable. th is pin should be tied directly to v dd for motorola bus format or direct ly to gnd for intel bus format. muxen 44 ? d in multiplexed bus enable. this pin should be tied directly to v dd for multiplexed bus mode or directly to gnd for non-multiplexed bus mode. int 42 25 d out interrupt service request. this pin provides notification to the host. *note: pins can be left unconnected when not used.
cp2200/1 rev. 1.0 11 cs 41 24 d in device chip select. rd /(ds) 39 22 d in read strobe (intel mode) or data strobe (motorola mode) wr /(r/w ) 40 23 d in write strobe (intel mode) or read/write strobe (motorola mode) d0/ad0 16 11 d i/o bit 0, non-multiplexed da ta bus or multiplexed address/data bus d1/ad1 17 12 d i/o bit 1, non-multiplexed da ta bus or multiplexed address/data bus d2/ad2 18 13 d i/o bit 2, non-multiplexed da ta bus or multiplexed address/data bus d3/ad3 19 14 d i/o bit 3, non-multiplexed da ta bus or multiplexed address/data bus d4/ad4 20 15 d i/o bit 4, non-multiplexed da ta bus or multiplexed address/data bus d5/ad5 21 16 d i/o bit 5, non-multiplexed da ta bus or multiplexed address/data bus d6/ad6 22 17 d i/o bit 6, non-multiplexed da ta bus or multiplexed address/data bus d7/ad7 23 18 d i/o bit 7, non-multiplexed da ta bus or multiplexed address/data bus a0 27* ? d in bit 0, non-multiplexed address bus a1 28* ? d in bit 1, non-multiplexed address bus a2 29* ? d in bit 2, non-multiplexed address bus a3/ale/(as) 32 ? d in bit 3, n on-multiplexed address bus ale strobe (multiplexed intel mode) address strobe (multiplexed motorola mode) ale/(as) ? 21 d in ale strobe (intel mode) address strobe (motorola mode) a4 33* ? d in bit 4, parallel interface non-multiplexed address bus a5 34* ? d in bit 5, parallel interface non-multiplexed address bus a6 37* ? d in bit 6, parallel interface non-multiplexed address bus a7 38* ? d in bit 7, parallel interface non-multiplexed address bus nc 1, 8, 11,12 24?26 35,36 47, 48 ? these pins should be left unconnected or tied to v dd . table 4. cp2200/1 pin definitions (continued) name pin numbers type description 48-pin 28-pin *note: pins can be left unconnected when not used.
cp2200/1 12 rev. 1.0 figure 4. 48-pin tqfp pinout diagram 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 nc nc a7 rd/(ds) wr/(r/w) muxen a2 a5 nc nc nc nc a1 vdd2 a6 d1/ad1 dgnd1 d2/ad2 vdd1 d0/ad0 nc d5/ad5 d4/ad4 a0 nc agnd av+ rx- rx+ nc tx+ tx- nc link rst d3/ad3 dgnd2 int cs nc xtal2 xtal1 act moten 13 14 15 16 17 18 19 20 21 22 23 24 d6/ad6 d7/ad7 a3/ale/(as) a4 cp2200 top view
cp2200/1 rev. 1.0 13 figure 5. 48-pin tqfp package dimensions e e1 d d1 48 1 a1 e b pin 1 identifier a2 a table 5. tqfp-48 package dimensions mm min typ max a??1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 d ? 9.00 ? d1 ? 7.00 ? e ? 9.00 ? e ? 0.50 ? e1 ? 7.00 ?
cp2200/1 14 rev. 1.0 figure 6. qfn-28 pinout diagram (top view) 4 5 6 7 2 1 3 11 12 13 14 9 8 10 18 17 16 15 20 21 19 25 26 27 28 23 22 24 CP2201 top view la agnd av+ rx- rx+ tx+ tx- rst ad0 vdd1 dgnd1 ad2 ad3 ad4 ad5 ad6 vdd2 ad7 ale/(as) rd/(ds) wr/(r/w) cs int moten xtal2 xtal1 gnd gnd ad1 dgnd2
cp2200/1 rev. 1.0 15 figure 7. qfn-28 package drawing table 6. qfn-28 package dimensions mm min typ max a 0.80 0.90 1.00 a1 0 0.02 0.05 a2 0 0.65 1.00 a3 ? 0.25 ? b 0.18 0.23 0.30 d?5.00? d2 2.90 3.15 3.35 e?5.00? e2 2.90 3.15 3.35 e?0.5? l 0.45 0.55 0.65 n?28? nd ? 7 ? ne ? 7 ? r0.09? ? aa ? 0.435 ? bb ? 0.435 ? cc ? 0.18 ? dd ? 0.18 ? 1 e d a2 a a1 e a3 e2 r e l bottom view side view 2 3 4 5 6 7 8 9 10 12 13 14 21 20 19 17 16 15 28 27 26 24 23 22 e2 25 2 d2 11 18 d2 2 6 x e 6 x e detail 1 detail 1 aa bb cc dd b
cp2200/1 16 rev. 1.0 figure 8. typical qfn-28 landing diagram optional gnd connection b l 0.50 mm 0.30 mm 0.10 mm 0.20 mm 0.85 mm 0.35 mm e e d 0.50 mm 0.30 mm 0.10 mm 0.20 mm 0.85 mm 0.35 mm top view e2 d2 0.20 mm 0.20 mm 0.50 mm 0.50 mm
cp2200/1 rev. 1.0 17 figure 9. typical qfn-28 solder paste diagram b l 0.50 mm 0.30 mm 0.10 mm 0.20 mm 0.85 mm 0.35 mm e e d 0.50 mm 0.30 mm 0.10 mm 0.20 mm 0.85 mm 0.35 mm top view e2 d2 0.20 mm 0.20 mm 0.50 mm 0.50 mm 0.30 mm 0.20 mm 0.60 mm 0.40 mm 0.70 mm 0.60 mm
cp2200/1 18 rev. 1.0 6. functional description 6.1. overview in most systems, the cp2200/1 is used for transmitting and receiving ethernet packets, non-volatile data storage, and controlling link and activity leds. the device is co ntrolled using direct and in direct internal registers accessible through the parallel host interface. all digital pins on the device are 5 v tolerant. 6.2. reset initialization after every cp2200/1 reset, the fo llowing initialization procedure is recommended to ensure proper device operation: step 1: wait for the reset pin to rise. this step takes the longest during a power-on reset. step 2: wait for oscillator initializ ation to complete. the host processo r will receive notification through the interrupt requ est signal once the oscillator has stabilized. step 3: wait for self init ialization to complete. the int0 interrupt status register on page 31 should be checked to determine when se lf initialization completes. step 4: disable interrupts (using int0en and int1en on page 33 and page 36) for events that will not be monitored or handled by the host processor. by de fault, all interrupts are enabled after every reset. step 5: initialize the physical layer. see ?15.7. init ializing the physical layer? on page 90 for a detailed physical layer init ialization procedure. step 6: enable the desired activity, link, or acti vity/link leds using the iopwr register on page 45. step 7: initialize the media access controller (mac). see ?14.1. initializing the mac? on page 78 for a detailed mac initia lization procedure. step 8: configure the receive filter. see ?12.4. initia lizing the receive buffer, filter and hash table? on page 59 for a detailed initialization procedure. step 9: the cp2200/1 is ready to transmit and receive packets. 6.3. interrupt request signal the cp2200/1 has an interrupt request signal (int ) that can be used to notify the host processor of pending interrupts. the int signal is asserted upon detection of any enabl ed interrupt event. host processors that cannot dedicate a port pin to the int signal can periodically poll the interrupt status registers to see if any interrupt generating events have occurred. if the /int signal is not used, pending interrupts such a receive fifo full must still be serviced. the 14 interrupt sources are listed below. interrupts are enabled on reset and can be disabled by software. pending interrupts can be cleared (allowing the int signal to de-assert) by reading the self-clearing interrupt registers. see ?8. interrupt sources? on page 30 for a complete description of the cp2200/1 interrupts. end of packet reached packet received receive fifo empty ?wake-on-lan? wakeup event receive fifo full link status changed oscillator initia lization complete jabber detected self initialization complete auto-negotiation failed flash write/erase complete remote fault notification packet transmitted auto-negotiation complete
cp2200/1 rev. 1.0 19 6.4. clocking options the cp2200/1 can be clocke d from an external parallel- mode crystal oscillator or cmos clock. figure 10 and figure 11 show typical connections for both clock source ty pes. if a crystal oscillator is chosen to clock the device, the crystal is started once the device is released from reset and remains on until the device reenters the reset state or loses power. figure 10. crystal oscillator example important note on external crystals: crystal oscillator circuits are quite sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device. the traces should be as short as possible and shielded with a ground plane from any other trac es that could introduce noise or interference. figure 11. external cmos clock example table 7 lists the clocking requirements of the cp2200/1 when us ing a crystal oscillator or cmos clock. table 8 shows the electrical characteristics of the xtal1 pin. th ese characteristics are useful when selecting an external cmos clock. xtal1 xtal2 10 m 20 mhz xtal1 xtal2 no connect 20 mhz cmos clock
cp2200/1 20 rev. 1.0 table 7. clocking requirements v dd = 3.1 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units frequency ? 20 ? mhz frequency error ? ? 50 ppm duty cycle 455055% table 8. input clock pin (xtal1) dc electrical characteristics v dd = 3.1 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units xtal1 input low voltage ? ? 0.7 v xtal1 input high voltage 2.0 ? ? v
cp2200/1 rev. 1.0 21 6.5. led control the cp2200/1 can be used to control link status and ac tivity leds. the cp2200 ( 48-pin tqfp) has two push-pull led drivers that can source up to 10 ma each. the cp22 01 (28-pin qfn) has a single push-pull led driver that turns the led on or off based on the link status and blin ks the led when activity is detected on a good link. table 9 shows the function of the led signals available on the cp2200/1. figure 12 shows a typical led connection for the cp2200. the CP2201 uses an identi cal connection for the la (link/activity) pin. the led drivers are enabled a nd disabled using the iopwr register on page 45. figure 12. led control example (cp2200) table 9. led control signals signal device description link cp2200 asserted when valid link pulses are detected. act cp2200 asserted for 50 ms for each packet transmitted or received. la CP2201 asserted when valid link pulses are detected and toggled for 50 ms for each packet transmitted or received. link act
cp2200/1 22 rev. 1.0 6.6. sending and receiving packets after reset initialization is complete , the cp2200/1 is ready to send and receive packets. packets are sent by loading data into the transmit buffer using the autowrite register and writing ?1? to txgo. see ?11.2. transmitting a packet? on page 48 for detailed information on how to tr ansmit a packet using the transmit interface. a packet transmitted interrupt will be generate d once transmission is complete. packet reception occurs automa tically when reception is enabled in th e mac and the receive buffer is not full. once a packet is received, the host proc essor is notified by generating a pack et received interrupt. the host may read the packet using the autoread interface. see ?12.2. reading a packet using the autoread interface? on page 58 and ?12.4. initializing the receive buffer, filter and hash table? on page 59 for additional information on using and initializing the receive interface.
cp2200/1 rev. 1.0 23 7. internal memory and registers the cp2200/1 is controlled through direct and indirect regi sters accessible through the pa rallel host interface. the host interface provides an 8-bit address space, of which there are 114 valid direct register locations (see table 11 on page 25). all remaining addresses in the memory spac e are reserved and should not be read or written. the direct registers provide access to the ram buffers, flash memory, indirect mac configuration registers, and other status and control registers for various device functions. figure 13 shows the ram and flash memory organization . the transmit and receive ram buffers share the same address space and are both accessed using the rama ddrh:ramaddrl pointer. each of the buffers has a dedicated data register. the flash memory has a sepa rate address space and a dedicated address pointer and data register. see ?13. flash memory? on page 73 for de tailed information on how to read and write to flash. figure 13. ram buffers and flash memory organization 7.1. random access to ram tr ansmit and receive buffers the most common and most efficient methods for accessing the transmit and receive buffers are the autowrite and autoread interfaces. these interfaces allow entire packe ts to be written or read at a time. in very few cases, the transmit and receive buffers may need to be accessed randomly. an example of this is a system in which a specific byte in the packet is checked to determine whether to read the packet or discard it. the following procedure can be used to read or write data to either ram buffer: step 1: write the address of the target byte to ramaddrh:ramaddrl. step 2: transmit buffer: read or write 8-bit data to ramtxdata to read or write from the target byte in the transmit buffer. receive buffer: read or write 8-bit data to ramrxdata to read or write from the target byte in the receive buffer. note: reads and writes of the ram buffers using the random access method are independent of the autoread and autowrite interfaces. each of the in terfaces has a dedicated set of address and data registers. see ?11.2. transmitting a packet? on page 48 and ?12.2. read ing a packet using the autoread interface? on page 58 for additional information about the autoread and autowrite interfaces. flash memory (8k) 0x0000 ? 0x1fff transmit buffer (2k) 0x0000 ? 0x07ff receive buffer (4k) 0x0000 ? 0x0fff ramaddrh:ramaddrl flashaddrh:flashaddrl
cp2200/1 24 rev. 1.0 register 1. ramaddrh: ram address pointer high byte register 2. ramaddrl: ram address pointer low byte register 3. ramtxdata: ram tran smit buffer data register register 4. ramrxdata: ram r eceive buffer data register bits7?0: ramaddrh: ram a ddress register high byte holds the most significant eight bits of the target ram address. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x08 bits7?0: ramaddrl: ram address register low byte holds the least significant eight bits of the target ram address. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x09 bits7?0: ramtxdata: transmit buffer data register read: returns data in the transmit bu ffer at location ramaddrh:ramaddrl. write: writes data to the transmit bu ffer at location ramaddrh:ramaddrl. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x04 bits7?0: ramrxdata: receive buffer data register read: returns data in the receive buffer at location ramaddrh:ramaddrl. write: writes data to the receive bu ffer at location ramaddrh:ramaddrl. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x02
cp2200/1 rev. 1.0 25 7.2. internal registers the cp2200/1 has 114 direct internal registers and 9 i ndirect registers. the registers are grouped into ten categories based on function. table 10 lists the regist er groups and provides links to the detailed register descriptions for each group. table 11 lists all direct registers available on the device. table 10. cp2200/1 register groups ram access registers section 7.1 on page 23 interrupt status and control registers section 8 on page 30 reset source registers section 9 on page 37 power mode registers section 10 on page 43 transmit status and control registers section 11.5 on page 49 receive interface status and contro l registers section 12.5 on page 60 receive buffer status and control registers section 12.7 on page 67 flash access registers section 13.3 on page 75 mac access registers section 14.2 on page 78 mac indirect registers section 14.3 on page 80 phy status and control registers section 15 on page 88 table 11. direct registers register address description page no. cpaddrh 0x21 current rx packet address high byte page 65 cpaddrl 0x22 current rx packet address low byte page 65 cpinfoh 0x1d current rx packet information high byte page 63 cpinfol 0x1e current rx packet information low byte page 64 cplenh 0x1f current rx packet length high byte page 64 cplenl 0x20 current rx packet length low byte page 64 cptlb 0x1a current rx packet tlb number page 67 flashaddrh 0x69 flash address pointer high byte page 76 flashaddrl 0x68 flash address pointe r low byte page 76 flashautord 0x05 flash auto read w/ increment page 77 flashdata 0x06 flash read/write data register page 77 flasherase 0x6a flash erase page 77 flashkey 0x67 flash lock and key page 76 flashsta 0x7b flash status page 75
cp2200/1 26 rev. 1.0 int0 0x63 interrupt status register 0 (self-clearing) page 31 int0en 0x64 interrupt enable register 0 page 33 int0rd 0x76 interrupt status register 0 (read-only) page 32 int1 0x7f interrupt status register 1 (self-clearing) page 34 int1en 0x7d interrupt enable register 1 page 36 int1rd 0x7e interrupt status register 1 (read-only) page 35 iopwr 0x70 port input/ output power page 45 macaddr 0x0a mac address pointer page 79 macdatah 0x0b mac data register high byte page 79 macdatal 0x0c mac data register low byte page 79 macrw 0x0d mac read/write initiate page 79 oscpwr 0x7c oscillator power page 46 phycf 0x79 physical layer configuration page 92 phycn 0x78 physical layer control page 91 physta 0x80 physical layer status page 93 ramaddrh 0x08 ram address pointer high byte page 24 ramaddrl 0x09 ram address pointer low byte page 24 ramrxdata 0x02 rxfifo ram data register page 24 ramtxdata 0x04 txbuff ram data register page 24 rsten 0x72 reset enable register page 42 rststa 0x73 reset source status register page 41 rxautord 0x01 rxfifo autoread w/ increment page 62 rxcn 0x11 receive control page 61 rxfifoheadh 0x17 receive buffer head pointer high byte page 71 rxfifoheadl 0x18 receive buffer head pointer low byte page 71 rxfifosta 0x5b receive buffer status page 72 rxfifotailh 0x15 receive buffer tail pointer high byte page 71 rxfifotaill 0x16 receive buffer tail pointer low byte page 71 rxfilt 0x10 receive filter configuration page 62 table 11. direct registers register address description page no.
cp2200/1 rev. 1.0 27 rxhashh 0x0e receive hash table high byte page 62 rxhashl 0x0f receive hash table low byte page 63 rxsta 0x12 receive status page 61 swrst 0x75 software reset register page 40 tlb0addrh 0x27 tlb0 addr ess high byte page 70 tlb0addrl 0x28 tlb0 address low byte page 70 tlb0infoh 0x23 tlb0 information high byte page 68 tlb0infol 0x24 tlb0 information low byte page 69 tlb0lenh 0x25 tlb0 length high byte page 69 tlb0lenl 0x26 tlb0 length low byte page 70 tlb1addrh 0x2d tlb1 addr ess high byte page 70 tlb1addrl 0x2e tlb1 address low byte page 70 tlb1infoh 0x29 tlb1 information high byte page 68 tlb1infol 0x2a tlb1 information low byte page 69 tlb1lenh 0x2b tlb1 length high byte page 69 tlb1lenl 0x2c tlb1 length low byte page 70 tlb2addrh 0x33 tlb2 addr ess high byte page 70 tlb2addrl 0x34 tlb2 address low byte page 70 tlb2infoh 0x2f tlb2 information high byte page 68 tlb2infol 0x30 tlb2 information low byte page 69 tlb2lenh 0x31 tlb2 length high byte page 69 tlb2lenl 0x32 tlb2 length low byte page 70 tlb3addrh 0x39 tlb3 addr ess high byte page 70 tlb3addrl 0x3a tlb3 address low byte page 70 tlb3infoh 0x35 tlb3 information high byte page 68 tlb3infol 0x36 tlb3 information low byte page 69 tlb3lenh 0x37 tlb3 length high byte page 69 tlb3lenl 0x38 tlb3 length low byte page 70 tlb4addrh 0x3f tlb4 addr ess high byte page 70 table 11. direct registers register address description page no.
cp2200/1 28 rev. 1.0 tlb4addrl 0x40 tlb4 address low byte page 70 tlb4infoh 0x3b tlb4 information high byte page 68 tlb4infol 0x3c tlb4 information low byte page 69 tlb4lenh 0x3d tlb4 length high byte page 69 tlb4lenl 0x3e tlb4 length low byte page 70 tlb5addrh 0x45 tlb5 addr ess high byte page 70 tlb5addrl 0x46 tlb5 address low byte page 70 tlb5infoh 0x41 tlb5 information high byte page 68 tlb5infol 0x42 tlb5 information low byte page 69 tlb5lenh 0x43 tlb5 length high byte page 69 tlb5lenl 0x44 tlb5 length low byte page 70 tlb6addrh 0x4b tlb6 addr ess high byte page 70 tlb6addrl 0x4c tlb6 address low byte page 70 tlb6infoh 0x47 tlb6 information high byte page 68 tlb6infol 0x48 tlb6 information low byte page 69 tlb6lenh 0x49 tlb6 length high byte page 69 tlb6lenl 0x4a tlb6 length low byte page 70 tlb7addrh 0x51 tlb7 addr ess high byte page 70 tlb7addrl 0x52 tlb7 address low byte page 70 tlb7infoh 0x4d tlb7 information high byte page 68 tlb7infol 0x4e tlb7 information low byte page 69 tlb7lenh 0x4f tlb7 length high byte page 69 tlb7lenl 0x50 tlb7 length low byte page 70 tlbvalid 0x1c tlb valid indicators page 68 txautowr 0x03 transmit data autowrite page 53 txbusy 0x54 transmit busy indicator page 51 txcn 0x53 transmit control page 51 txendh 0x57 transmit data ending address high byte page 53 txendl 0x58 transmit data ending address low byte page 53 table 11. direct registers register address description page no.
cp2200/1 rev. 1.0 29 txpauseh 0x55 transmit pause high byte page 52 txpausel 0x56 transmit pause low byte page 52 txpwr 0x7a transmitter power page 46 txsta0 0x62 transmit status vector 0 page 57 txsta1 0x61 transmit status vector 1 page 56 txsta2 0x60 transmit status vector 2 page 56 txsta3 0x5f transmit status vector 3 page 55 txsta4 0x5e transmit status vector 4 page 55 txsta5 0x5d transmit status vector 5 page 54 txsta6 0x5c transmit status vector 6 page 54 txstarth 0x59 transmit data starting address high byte page 52 txstartl 0x5a transmit data starting address low byte page 52 vdmcn 0x13 v dd monitor control register page 39 table 11. direct registers register address description page no.
cp2200/1 30 rev. 1.0 8. interrupt sources the cp2200/1 can alert the host processo r when any of the 14 interrupt source events listed in table 12 triggers an interrupt. the cp2200/1 alerts the host by setting the appropriate flags in the interrupt status registers and driving the int pin low. the int pin will remain asserted until all interr upt flags for enabled interrupts have been cleared by the host. interrupt flags ar e cleared by reading the self-clearing interrupt status registers, int0 and int1. interrupts can be disabled by clearing the corresponding bits in int0en and int1en. if the host processor do es not utilize the int pin, it can periodically read the interrupt status r egisters to determine if any interrupt-generating events have occurred. the int0rd and int1rd read-only registers provide a method of checking for interrupts without clearing the interrupt status registers. table 12. interrupt source events event description pending flag enable flag end of packet the last byte of a packet has been read from the receive buffer using the autoread interface. int0.7 int0en.7 receive fifo empty the last packet in the receive buffer has been unloaded or discarded. int0.6 int0en.6 self initialization complete th e device is ready for rese t initialization. see ?6.2. reset initialization? on page 18. int0.5 int0en.5 oscillator initialization comp lete the external oscillator has stabilized. int0.4 int0en.4 flash write/erase complete a flash write or erase operation has completed. int0.3 int0en.3 packet transmitted the transmit interface has transmitted a packet. int0.2 int0en.2 receive fifo full the receive buffer is full or the maximum number of packets has been exceeded. decode the rxfifosta status register to determine the receive buffer status. int0.1 int0en.1 packet received a packet has been added to the receive buffer. int0.0 int0en.0 ?wake-on-lan? wakeup event the device has been connected to a network. int1.5 int1en.5 link status changed the device has been connected or disconnected from the network. int1.4 int1en.4 jabber detected the transmit interface has detected and responded to a jabber condition. see ieee 802 .3 for more information about jabber conditions. int1.3 int1en.3 auto-negotiation failed an auto-negotiation attempt has failed. software should check for a valid link and re-try auto-negotiation. int1.2 int1en.2 reserved auto-negotiation complete an auto-negotiation attempt has completed. this inter- rupt only indicates completi on, and not success. occa- sionally, auto-negotiation a ttempts will not complete and/or fail; therefore, a 3 to 4 second timeout should be implemented. a successful auto-negotiation attempt is one that complete s without failure. int1.0 int1en.0
cp2200/1 rev. 1.0 31 register 5. int0: interrupt stat us register 0 (self-clearing) note: reading this register will clear all int0 interrupt flags. bit 7: eopint: end of packet interrupt flag 0: the last byte of a packet has not been read since the last time eopint was cleared. 1: the last byte of a packet has been read. bit 6: rxeint: receive fifo empty interrupt flag 0: the receive fifo has not been empty si nce the last time rxeint was cleared. 1: the receive fifo is empty. bit 5: selfint: self initializat ion complete interrupt flag 0: self initialization has not completed since the last time selfint was cleared. 1: self initializat ion has completed. bit 4: oscint: oscillator initializ ation complete interrupt flag 0: oscillator initialization ha s not completed sinc e the last time oscint was cleared. 1: oscillator initializ ation has completed. bit 3: flweint: flash write/erase operation complete interrupt flag 0: a flash write or erase operation has not completed since the last time flweint was cleared. 1: a flash write or erase operation has completed. bit 2: txint: packet transmitted interrupt flag 0: a packet transmission has not complete d since the last time txint was cleared. 1: a packet has been transmitted. bit 1: rxfint: receive fifo full interrupt flag 0: the receive fifo has not been full si nce the last time rxfint was cleared. 1: the receive fifo is full. bit 0: rxint: packet received interrupt flag 0: a packet has not been added to the receiv e buffer since the last time rxint was cleared. 1: a packet has been added to the receive buffer. rc rc rc rc rc rc rc rc reset value eopint rxeint selfint oscint flweint txint rxfint rxint 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x63
cp2200/1 32 rev. 1.0 register 6. int0rd: interrupt st atus register 0 (read-only) note: reading this register will not clear int0 interrupt flags. bit 7: eopintr: end of packet read-only interrupt flag 0: the last byte of a packet has not been read since the last time eopif was cleared. 1: the last byte of a packet has been read. bit 6: rxeintr: receive fifo empty read-only interrupt flag 0: the receive fifo has not been empty since the last time rxfifoe was cleared. 1: the receive fifo is empty. bit 5: selfintr: self in itialization complete re ad-only interrupt flag 0: self initialization has not completed since the last time selfint was cleared. 1: self initializat ion has completed. bit 4: oscintr: oscillator initialization complete read-only in terrupt flag 0: oscillator initialization ha s not completed sinc e the last time oscint was cleared. 1: oscillator initializ ation has completed. bit 3: flweintr: flash write/erase operation complete read-only interrupt flag 0: a flash write or erase operation has not completed since the last time flweint was cleared. 1: a flash write or erase operation has completed. bit 2: txintr: packet transmitted read-only interrupt flag 0: a packet transmission has not complete d since the last time txint was cleared. 1: a packet has been transmitted. bit 1: rxfintr: receive fifo full read-only interrupt flag 0: the receive fifo has not been full si nce the last time rxfint was cleared. 1: the receive fifo is full. bit 0: rxintr: packet receiv ed read-only interrupt flag 0: a packet has not been added to the receiv e buffer since the last time rxint was cleared. 1: a packet has been added to the receive buffer. rrrrrrrrreset value eopintr rxeintr selfintr oscintr flwe intr txintr rxfintr rxintr 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x76
cp2200/1 rev. 1.0 33 register 7. int0en: interr upt enable register 0 bit 7: eeopint: enable end of packet interrupt 0: disable end of packet interrupt. 1: enable end of packet interrupt. bit 6: erxeint: enable rece ive fifo empty interrupt 0: disable receive fi fo empty interrupt. 1: enable receive fi fo empty interrupt. bit 5: eselfint: enable self init ialization comple te interrupt 0: disable self initializ ation complete interrupt. 1: enable self initializ ation complete interrupt. bit 4: eoscint: enable oscillator in itialization complete interrupt 0: disable oscillator initia lization comple te interrupt. 1: enable oscillato r initialization co mplete interrupt. bit 3: eflweint: enable flash write/erase operation complete interrupt 0: disable flash write/erase operation complete interrupt. 1: enable flash write/erase operation complete interrupt. bit 2: etxint: enable packe t transmitted interrupt 0: disable packet transmitted interrupt. 1: enable packet tr ansmitted interrupt. bit 1: erxfint: enable receive fifo full interrupt 0: disable receive fifo full interrupt. 1: enable receive fifo full interrupt. bit 0: erxint: enable pa cket received interrupt 0: disable packet received interrupt. 1: enable packet re ceived interrupt. r/w r/w r/w r/w r/w r/w r/w r/w reset value eeopint erxeint eselfint eoscint eflwe int etxint erxfint erxint 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x64
cp2200/1 34 rev. 1.0 register 8. int1: interrupt stat us register 1 (self-clearing) note: reading this register will clear all int1 interrupt flags. bits 7?6: unused. read = 00b, write = don?t care. bit 5: wakeint: ?wake-on- lan? interrupt flag 0: the device has not b een connected to a netw ork since the last time wakeint was cleared. 1: the device has been connec ted to a network since the la st time wakeint was cleared. bit 4: linkint: link status changed interrupt flag 0: the link status has not changed since the last time linkint was cleared. 1: the link status has changed (device has been connected or removed from a network). bit 3: jabint: jabber detected interrupt flag 0: a jabber condition has not been detected since the last time jabint was cleared. 1: a jabber condition has been detected. bit 2: anfint: auto-negotiation failed interrupt flag 0: auto-negotiation has not failed sinc e the last time anfint was cleared. 1: auto-negotiation has failed. bit 1: reserved: read = 0. bit 0: ancint: auto-negotiat ion complete interrupt 0: auto-negotiation has not completed since the last time ancint was cleared. 1: auto-negotiation has completed. r/w r/w rc rc rc rc rc rc reset value ? ? wakeint linkint jabint reserved rfint ancint 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x7f
cp2200/1 rev. 1.0 35 register 9. int1rd: interrupt st atus register 1 (read-only) note: reading this register will not clear int1 interrupt flags. bits 7?6: unused. read = 00b, write = don?t care. bit 5: wakeintr: ?wake-on-lan? read-only interrupt flag 0: the device has not b een connected to a netw ork since the last time wakeint was cleared. 1: the device has been connec ted to a network since the la st time wakeint was cleared. bit 4: linkintr: link status changed read-only interrupt flag 0: the link status has not changed since the last time linkint was cleared. 1: the link status has changed (device has been connected or removed from a network). bit 3: jabintr: jabber detected read-only interrupt flag 0: a jabber condition has not been detected since the last time jabint was cleared. 1: a jabber condition has been detected. bit 2: anfintr: auto-negotiation failed read-only interrupt flag 0: auto-negotiation has not failed sinc e the last time anfint was cleared. 1: auto-negotiation has failed. bit 1: reserved: read = 0b. bit 0: ancintr: auto-neg otiation complete re ad-only interrupt flag 0: auto-negotiation has not completed since the last time ancint was cleared. 1: auto-negotiation has completed. r/wr/wr rrrrrreset value ? ? wakeintr linkintr jabintr anfin tr reserved ancintr 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x7e
cp2200/1 36 rev. 1.0 register 10. int1en: interr upt enable register 1 bits 7?6: unused. read = 00b, write = don?t care. bit 5: ewakeint: enable ?wake-on-lan? interrupt 0: disable ?wake-on-lan? interrupt. 1: enable ?wake-on-lan? interrupt. bit 4: elinkint: enable link status changed interrupt 0: disable link status changed interrupt. 1: enable link status changed interrupt. bit 3: ejabint: enable jab ber detected interrupt 0: disable jabber detected interrupt. 1: enable jabber detected interrupt. bit 2: eanfint: enable auto-negotiation failed interrupt 0: disable auto-negotia tion failed interrupt. 1: enable auto-negoti ation failed interrupt. bit 1: reserved: read = 0b. must write 0b. bit 0: eancint: enable auto-nego tiation complete interrupt 0: disable auto-negotiati on complete interrupt. 1: enable auto-negotiat ion complete interrupt. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ewakeint elinkint ejabint ean fint reserved eancint 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x7d
cp2200/1 rev. 1.0 37 9. reset sources reset circuitry allows the cp2200/1 to be easily placed in a predefined default condition. upon entry to this reset state, the following events occur: all direct and indirect registers are in itialized to their defined reset values. digital pins (except /rst) are forced into a high impedance state with a weak pull-up to v dd . analog pins (tx+/tx?, rx+/rx?) are forced into a high impedance state without a weak pull-up. the external oscillator is stopped and /rst driven low (except on a software reset). all interrupts are enabled. the contents of the transmit and receive buffers are unaf fected by a reset as long as the device has maintained sufficient supply voltage. however, since the buffer pointers are reset to their default val ues, the data is effectively lost unless the host processor has kept track of the starting address and length of each packet in the buffer. the cp2200/1 has five reset sources that place the device in the reset state. the method of entry to the reset state determines the amount of time spent in reset and the behav ior of the /rst pin. each of the following reset sources is described in the following sections: power-on power-fail oscillator-fail external /rst pin software command upon exit from the reset state, the device automatically starts the external oscillator and waits fo r it to settle (this step is skipped on software reset). once the crystal oscillator settles, the osc illator initialization complete interrupt occurs (interrupt pin asserted), and the host processor may now access the internal registers to poll for the self initialization complete interrupt. if the host does not have acce ss to the interrupt signal, it should wait approximately 1 ms after the risi ng edge of reset pin prior to polling the internal register s. note that the reset pin could remain low up to 100 ms depending on the power supply ramp time. the device is fully functional after the self initialization has comp leted. see ?6.2. reset initialization? on page 18 for the recommended initialization procedure following a device reset.
cp2200/1 38 rev. 1.0 9.1. power-on reset during power-up, the cp2200/1 is held in the reset state, and the /rst pin is driven low until v dd settles above v rst . a delay (t pordelay ) occurs between the time v dd reaches v rst and the time the device is released from reset; the typical delay is 5 m s. refer to table 13 for the electrical characteristics of the power supply monitor circuit. figure 14. reset timing power-on reset vdd monitor reset /rst t volts 1.0 logic high logic low t pordelay v d d v rst vdd
cp2200/1 rev. 1.0 39 9.2. power-fail when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the /rst pin low and return the cp2200/1 to the reset state. when v dd returns to a level above v rst , the cp2200/1 will be released from the re set state as shown in figure 14. the power supply monitor circuit (v dd monitor) is enabled and selected as a reset source by hardware following every power-on reset. to prevent the device from being held in reset when v dd drops below v rst , the v dd monitor may be deselected as a reset source (see rsten on page 42) and disabled (see vdmcn on page 39). it is recommended to leave the v dd monitor enabled and selected as a reset source at all times. register 11. vdmcn: v dd monitor cont rol register 9.3. oscill ator-fail reset if the system clock derived from the oscillator fails for any reason after oscillator initializ ation is comple te, the reset circuitry will drive the /rst pin low an d return the cp2200/1 to the reset state. the cp 2200/1 will remain in the reset state for approximately 1 ms then exit the reset stat e in the same manner as th at for the power-on reset. 9.4. external pin reset the external /rst pin provides a means for external circui try to force the cp2200/1 into a reset state. asserting the /rst pin low will cause the cp2200/1 to enter the reset state. it is recomme nded to provide an external pull-up and/or decoupling capacitor of the /rst pin to avoid er roneous noise-induced resets . the cp2200/1 will exit the reset state approximately 4 s after a logic high is detected on /rst. bit 7: vdmen: v dd monitor enable this bit can be used to disable or enable the v dd monitor circuit. note: the v dd monitor circuit is enabled and selected as a reset source following every power-on reset . if the v dd monitor is disabled and then reenabled during device oper ation, it must be allowed to stabilize before it is selected as a reset source. selecting the v dd monitor as a reset source before it has stabilized will generate a system reset. see table 13 on page 42 for the minimum v dd monitor turn-on time . 0: v dd monitor disabled. 1: v dd monitor enabled. bit6: vddstat: v dd status this bit indicates the current power supply status (v dd monitor output). 0: v dd voltage is at or below the v dd monitor threshold. 1: v dd voltage is above the v dd monitor threshold. bits 5?0: reserved. read = varies; write = don?t care. r/wr/wrrrrrrreset value vdmen vddstat reserved reserved reserved reserved reserved reserved 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x13
cp2200/1 40 rev. 1.0 9.5. software reset the software reset provides the host cpu the ability to reset the cp2200/1 through the parallel host interface. writing a ?1? to reset (swrst.2) will force the device to enter the reset state with the exception that the external oscillator will not be stopped. as soon as the device enters the reset stat e, it will immediately exit the reset state and start device calibration; the osc illator initialization comp lete interrupt is not be generated. after self initialization is complete, the device is fully functional. note: the software reset is enabled after every reset; however, it may be de-selected as a rese t source (see the register description for rsten on page 42). register 12. swrst: software reset register bits 7?3: unused. read = 00000b, write = don?t care. bit 2: reset: software reset initiate writing a ?1? to this bit will generate a software reset. bits 1?0: unused. read = 00b, write = don?t care. r\w r\w r/w r/w r/w w r/w r/w reset value ? ? ? ? ? reset ? ? 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x75
cp2200/1 rev. 1.0 41 9.6. determining the source of the last reset the rststa register can be used to determine the cause of the last reset. note: if the porsi bit is set to logic 1, all other bits in rststa are undefin ed. it is impossible to differentiate between a power-on, power-fail, and oscillator-fail reset by read ing the rststa register. register 13. rststa: reset source status register bits 7?3: unused. read = 00000b, write = don?t care. bit 2: swrsi: software reset indicator 0: source of last reset was not a write to reset (swreset.2). 1: source of last reset was a write to reset (swreset.2). bit 1: porsi: power-on / power-fail / oscillator-fail reset indicator 0: source of last reset was not a power- on, power-fail, or oscillator-fail event. 1: source of last reset was a power- on, power-fail, or oscillator-fail event. bit 0: pinrsi: external pin reset indicator 0: source of last rese t was not the /rst pin. 1: source of last re set was the /rst pin. r/w r/w r/w r/w r/w r r r reset value ? ? ? ? ? swrsi porsi pinrsi 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x73
cp2200/1 42 rev. 1.0 9.7. de-selecting interrupt sources the power-fail (v dd monitor) reset is automatically enabled after every power-on reset. the software reset is enabled after every device reset, regardless of the reset source. the rsten register c an be used to prevent either of these two reset sources from generating a device reset. register 14. rsten: reset enable register table 13. reset electrical characteristics v dd = 3.1 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units rst output low voltage iol = 8.5 ma ? ? 0.6 v rst input high voltage 0.7 x v dd ??v rst input low voltage ? ? 0.3 x v dd v rst input pullup current ? 25 50 a v dd por threshold (vrst) 2.2 2.4 2.6 v minimum /rst low time to generate a system reset 15 ? ? s v dd monitor turn-on time 100 ? ? s v dd monitor supply current ? 20 50 bits 7?3: unused. read = 00000b, write = don?t care. bit 2: eswrst: enable software reset 0: software reset is not selected as a reset source. 1: software reset is selected as a reset source. bit 1: epfrst: enable power fail reset 0: the power fail detection circuitry (v dd monitor) is not select ed as a reset source. 1: the power fail detection circuitry (v dd monitor) is selected as a reset source. bit 0: unused. read = 0b, write = don?t care. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? eswrst epfrst ? 00000100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x72
cp2200/1 rev. 1.0 43 10. power modes the cp2200/1 has four power modes that can be used to minimize overall system power consumption. the power modes vary in device functionality and recovery methods. each of the following power modes is explained in the following sections: normal mode (device fully functional) link detection mode (transmitter disabled) memory mode (transmitter and receiver disabled) shutdown mode (oscilla tor output disabled) the power modes above are achieved by disabling specif ic primary functions of the cp2200/1. figure 15 shows how power is distributed throughout the cp2200/1. to further reduce power consumption in any of the power modes, secondary device functions ma y be turned off individually. the se condary device functions that may be turned off are: link/activity led drivers weak pull-ups to v dd v dd monitor figure 15. power and clock distribution control vdd system clock (oscillator) parallel host interface tx and rx buffers mac flash memory vdd monitor phy transmitter receiver vdmcn.7 oscpwr.0 phycn.7 txen (phycn.6) rxen (phycn.5) iopwr activity led link led weak pullups all digital pins link (la) pin act pin
cp2200/1 44 rev. 1.0 10.1. normal mode normal mode should is used whenever the host is sending or receiving pa ckets. in this mode, the cp2200/01 is fully functional. typical norma l mode power consumption is listed in table 2 on page 9. note: when in normal mode, the transmitter has a power saving mode which is enabled on reset. this power saving mode dis- ables the transmitter's output driver an d placed the tx+/- pins in high impedance when the cp220x is not transmitting link pulses or data. to meet the minimum transmitter loss r equirements in ieee 802.3, this power saving mode should be disabled. see register 17, ?txpwr: transmitter power register,? on page 46 for details. 10.2. link detection mode in link detection mode, the transmitte r and link pulse gen eration logic is disabled. t he cp2200/1 will appear to be ?offline? because link pulses will not be generated. the most common way to use link detection mode is enabling the wake-on-lan interrupt, placing the cp2200/01 into li nk detection mode, then placing the mcu in a low power mode until the system is plugged into a network. note: when using link detection mode, the user should ensure that the link partner is always transmitting link pulses. an exam- ple of this type of device would be a hub or a switch. some notebook pcs implement a power saving feature in which they stop transmitting link pulses if a valid link is not detect ed. this would create a situation where both link partners are waiting for each other to start transmitting link pulses. note: a minimum transmitter return lo ss is specified in ieee 802.3. if the transmitter is disabled, the tx pins are placed in high impedance mode and do not create the minimum return lo ss. the transmitter should not be disabled if the device is considered "on a network" and valid link pulses are being received. from normal mode, the device can be placed in link detection mode by clearing txen (phycn.6) to ?0?. to return the device to normal mode, di sable the physical layer by clearin g phycn to 0x00, then re-enable the physical layer using the startup procedure in section 15.7 on page 90. 10.3. memory mode in memory mode, the physical layer (receiver and transmi tter) is placed in a low-power state, and the cp2200/1 can neither send nor receive packets. the only primary functi ons of the device that remain functional are the flash memory and ram buffers. the ram buffers are only accessible using the random access method described in section 7.1 on page 23. the device can be placed in memory mode by clearing the three most significant bits of the phycn register to ?000?. the device can be returned to normal mode by setti ng the three most significant bits of the phycn register to ?111? and waiting the appropriate physical layer turn-on times for both the transmitter and the receiver. the physical layer electrical characterist ics including turn-on time are specified in table 22 on page 93. to return the device to normal mode, disable the physical layer by clearing phycn to 0x00, then re-enable the physical layer using the startup procedure in section 15.7 on page 90. 10.4. shutdown mode shutdown mode is the lowest power mode for the cp2200/ 1. all primary and secondary functions are disabled, and the system clock is disconnected from the oscillato r. the device can recover from shutdown mode only through a power-on or pin reset. the device can be placed in shutdown mode using the following procedure: step 1: disable the phy by clearing the thr ee most significant bits of phycn to ?000?. step 2: disable the led drivers by clearing bits 2 and 3 of iopwr to ?00?. step 3: disable the v dd monitor (optional) by cleari ng vdmen (vdmcn.7) to ?0?. step 4: disconnect the oscillator outp ut from the rest of the device by clearing oscoe (oscpwr.0) to ?0?. this step should be performed la st because the device will no longer respond until th e next pin or power-on reset.
cp2200/1 rev. 1.0 45 10.5. disabling s econdary device functions the led drivers, weak pull-ups, and v dd monitor can be disabled to minimi ze power consumption. the typical supply current for the v dd monitor is specified in table 13 on page 42. disabling weak pull-ups will save current if the moten and muxen pins are tied to ground, but w ill cause the address and data pins to float (causing undefined device behavior and increased power consumption) if they are not externally driven or pulled to a defined logic level using pull-up or pull-down resistors. th e internal weak pull-ups should not be disabled unless all digital pins are externally driven to a logic high or logic low state. register 15. iopwr: port in put/output power register bits 7?4: unused. read = 0000b, write = don?t care. bit 3 acten: activity led enable 0: activity led disabled. 1: activity led enabled. bit 2 linken: link led enable (link/activity led on CP2201) 0: link (link/activity) led disabled. 1: link (link/activity) led enabled. bit 1: weakd: weak pull-up disable 0: weak pull-ups are enabled. 1: weak pull-ups are disabled. bit 0: reserved. read = 0b; must write 0b. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? acten linken weakd reserved 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x70
cp2200/1 46 rev. 1.0 register 16. oscpwr: osci llator power register register 17. txpwr: transmitter power register bits 7?5: unused. read = 0000b, write = don?t care. bit 4?2: reserved. read = 1 00b; must wr ite x00b. bit 1: unused. read = 1b; write = don?t care. bit 0: oscoe: oscilla tor output enable this bit controls the output of the external oscillator. it does not affect the external crystal driver. 0: oscillator output disabled . the device will no longer re spond until the next reset. 1: oscillator output enabled. r/w r/w r/w r/w r/w r/w r r/w reset value ? ? ? reserved reserved reserved reserved oscoe 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x7c bit 7: psaved. transmitter powe r save mode disable bit 0: enable transmitter power saving mode. 1: disable transmitter power saving mode. bits 6?0: reserved. read = varies; must write 0000000b. r/w r/w r/w r/w r/w r/w r/w r/w reset value psaved reserved reserved reserved reserved reserved reserved reserved 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x7a
cp2200/1 rev. 1.0 47 11. transmit interface 11.1. overview the cp2200/1 provides a simple interface for transmitting ethernet packets requiring the host to only load the source and destination ad dresses, length /type, and data into the transmit buffer . all other ieee 802.3 requirements, such as the preamble, start frame delimiter, crc, and padding (full-duplex only), are automatically generated. figure 16 shows a typical ethernet packet. figure 16. typical ethernet packet crc (4 bytes) preamble and start frame delimiter (8 bytes) destination mac address (6 bytes) source mac address (6 bytes) length/type (2 bytes) data (46 to 1500 bytes) (automatically padded with zeros if less than 46 bytes) obtained from transmit buffer ethernet frame (minimum 64 bytes)
cp2200/1 48 rev. 1.0 11.2. transmitting a packet once reset initialization is complete (see ), the cp2200/1 is ready to transmit ethernet packets. the following procedure can be used to transmit a packet: step 1: wait for the previous packet to complete (t xbusy == 0x00). the worst ca se time to transmit a packet is 500 ms in half-duplex mode with exponential backoff. step 2: set the txstarth:txstartl transmit buffer pointer to 0x0000. step 3: if the last packet was aborted ((txsta3 & 0xf8 ) != 0x00), then this packet must be loaded into the transmit buffer using the random memory access method: a. set ramaddrh:ramaddrl to 0x0000. b. write the first data byte to ramtxdata. c. increment ramaddrh:ramaddrl. d. write another data byte to ramtxdata. e. repeat steps c and d until the entire packet is loaded. f. pad small packets to at least 64 bytes. g. set txendh:txendl to the address of the last by te added. this value must be greater than or equal to 0x0040. step 4: if the last packet was succes sfully transmitted ((txsta2 & 0x80) == 0x80), then this packet may be loaded into the transmit buffer using the autowrite interface: a. write all data bytes to the txau towr register, one byte at time. b. if the mac is in half-duplex mode, pad small packets to at least 64 bytes. step 5: set the txstarth:txstartl tran smit buffer pointer back to 0x0000. step 6: write a ?1? to the txgo bi t (txcn.0) to beg in transmission. note: step 4 may be skipped if step 3 is always performed. 11.3. overriding transmit configuration options the global transmit configuration options are set in the mac registers. the transmit interface allows the host processor to customize packet transmission on a per-packe t basis by overriding the global mac settings. the following options can be overridden by the transmit interface: short frame padding?when enabled, ensures that no fram e smaller than 64 bytes is transmitted. the frame size does not include the 8 byt e preamble; however, the 4- byte crc field is included. crc generation?when en abled, a 32-bit crc will be calculated and appended to th e ethernet frame. pause packet transmission (full duplex mode)?when en abled, an ethernet pause packet with a pause value of txpauseh:txpausel is transmitted. the pause value is in units of 512 bit times (51.2 s). application of back pressure (half duplex mode). switching between half/full duplex modes. note: th is setting does not affect the physical layer. 11.4. transmit buffer and autowrite interface the transmit buffer provides the autowrit e interface to efficiently load the buf fer with an entire packet. the interface consists of three registers: txstart, txend, and t xautowr. the txstart register points to the address of the next available byte and can be rese t to the first byte of the buffer. txend points to the last byte added to the buffer. txautowr is the data register. each write to txautowr sets txend to the address of the byte written and increments txstart. after the packet is loaded into the buffer, txstart is reset to 0x0000 to mark the starting point of the packet. txend will continue to point to the last byte in the packet. note: the autowrite interface cannot be used following an aborte d packet. this only applies if the device is in half-duplex mode.
cp2200/1 rev. 1.0 49 11.5. transmit status and control registers the cp2200 transmit interface is controlled and managed through the registers in table 14. after each packet is transmitted, information about the last transmitted packe t can be obtained from the 52-bit transmit status vector accessible through the txsta0 ? txsta6 registers. the transmit status vector is described in table 15. table 14. transmit status and control register summary register long name address description txcn transmit control 0x53 contains the transmit configuration option over- ride bits and the txgo bit used to start packet transmission. txbusy transmit busy indicator 0x54 read-only register returning 0x01 when transmit interface is currently transmitting a packet and 0x00 when transmit interface is not transmitting. txpauseh txpausel transmit pause high and low bytes 0x55 0x56 16-bit pause value used for pause packet transmission. the pause value is in units of 512 bit times (51.2 s). txstarth txstartl transmit data starting address high and low bytes 0x59 0x5a starting address of outgoing packet in the trans- mit buffer. packets added to the transmit buffer must start at 0x0000. txendh txendl transmit data ending address high and low bytes 0x57 0x58 address of last byte added to the transmit buffer. this register is managed by hardware. txautowr transmit data autowrite 0x03 writes to this register add a byte to the transmit buffer, set txend to the address of the written byte, and increment txstart. txsta6 txsta5 txsta4 txsta3 txsta2 txsta1 txsta0 transmit status vector 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 52-bit transmit status vector containing informa- tion about the last transmitted packet including collision count, successfu l transmission, total bytes transmitted, etc.
cp2200/1 50 rev. 1.0 table 15. transmit status vector description bit field name description 51 transmitted vlan frame last frame transmit ted had length/type field of 0x8100 (vlan protocol identifier). 50 back pressure applied back pressure was applied during transmission. 49 transmitted pause frame last frame transmitted was a valid pause control frame. 48 transmitted control frame last frame transmitted was a control frame. 47-32 total bytes transmitted number of bytes tr ansmitted on wire including all bytes from collided attempts. 31 transmit under-run last packet was aborted due to a data under-run condition. 30 jumbo packet detected last packet was aborted due to the detection of a jumbo packet (oversized frame). jumbo packets are not supported. 29 late collision detected last packet was abor ted due to a collision occurring after the 51.2 s collision window. 28 excessive collisions detected last packet was a borted due to det ection of 16 or more colli- sions. 27 excessive delay detected aborted due to a delay longer than 2.42ms. 26 delay detected last packet was transmitted, but had delay (less than 2.42 ms). 25 transmitted broadcast packet last packet tran smitted had a broadcast destination address. 24 transmitted multicast packet last packet tran smitted had a multicast destination address. 23 transmit successful last packe t was successfully transmitted. 22 type field detected last packet?s length/t ype field had a value greater than 1500. 21 length check error last packet?s length/type field had a value less than or equal to 1500 which did not match the actual frame length. 20 crc error last packet?s crc field did not match the inte rnally generated crc. 19-16 transmit collision count number of collisi ons encountered during transmission of the last packet. 15-0 transmit byte count numbe r of bytes in last frame not counting collided bytes.
cp2200/1 rev. 1.0 51 register 18. txcn: tran smit control register register 19. txbusy: transmit busy indicator bit 7: ovrride: default override 0: settings for bits 5, 4, 3, 2, and 1 in txcn will be ignored. mac settings will take effect. 1: settings for bits 5, 4, 3, 2, and 1 in tx cn will be applied. mac settin gs will be overridden. bit 6: unused. read = 0b, write = don?t care. bit 5: crcenov: crc enable 0: disable crc append on transmission. 1: enable crc append on transmission. bit 4: padenov: pad enable 0: disable padding of short frames. 1: enable padding of short frames. bit 3: txppkt: transmit a pause control packet 0: normal packet transmissi on. packet data will be obtained from the transmit buffer. 1: a pause control packet with the value of tx pauseh:txpausel will be transmitted. data in the transmit buffer will not be accessed. pause contro l packets are only valid in full-duplex mode. bit 2: bckpres: apply back pressure 0: normal packet transmission. back pressure will not be applied. 1: back pressure will be applie d on transmission (only valid in half duplex mode). bit 1: fdplxov: full duplex operation note: the transmit interface, mac, and physical layer must be configured to the same duplex mode. 0: transmit interface operates in half duplex mode. 1: transmit interface operates in full duplex mode. bit 0: txgo: transmit packet set this bit to ?1? to begi n transmission of a packet. note: txgo should not be set to one if both txstart and txend are zero (i.e., no data has been added to the buffer). r/w r/w r/w r/w r/w r/w r/w w reset value ovrride ? crcenov padenov txppkt bckpres fdplxov txgo 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x53 bits 7?1: unused. read = 0000000b, write = don?t care. bit 0: txbusy: packet transmit status 0: packet transmit is not in progress. 1: packet transmit is in progress. rrrrrrrrreset value ? ? ? ? ? ? ? txbusy 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x54
cp2200/1 52 rev. 1.0 register 20. txpauseh: transmit pause high byte register 21. txpausel: transmit pause low byte register 22. txstarth: transmit data starting address high byte register 23. txstartl: transmit data starting address low byte bits 7?0: txpauseh: transmit pause high byte high byte of the 16-bit pause value sent in a pau se control packet. the pause value is in units of 512 bit times (512 bit times = 51.2 s). r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x55 bits 7?0: txpausel: transmit pause low byte low byte of the 16-bit pause value sent in a pau se control packet. the paus e value is in units of 512 bit times (512 bit times = 51.2 s). r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x56 bits 7?0: txstarth: transmit data starting address high byte high byte of the starting address of outgoing packet in the transmit buffer . note: outgoing packets must start at 0x0000. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x59 bits 7?0: txstartl: transmit da ta starting address low byte low byte of the starting address of outgoing pack et in the transmit buffer . note: outgoing packets must start at 0x0000. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x5a
cp2200/1 rev. 1.0 53 register 24. txendh: transmit data ending address high byte register 25. txendl: transmit data ending address low byte register 26. txautowr: transmit data autowrite bits 7?0: txendh: transmit data ending address high byte high byte of the address of the last byte added to the transmit buffer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x57 bits 7?0: txendl: transmit data ending address low byte low byte of the address of the last byte added to the transmit buffer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x58 bits 7?0: txstartl: transmit da ta starting address low byte writes to this register add a si ngle byte to the transmit buffer and set the txend pointer to the address of the byte currently being written. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x03
cp2200/1 54 rev. 1.0 register 27. txsta6: transmit status vector 6 register 28. txsta5: transmit status vector 5 note: this register contains bits 51? 48 of the transmit status vector. bits 7?4: unused. read = 0000b, write = don?t care. bit 3. txvlan: transmitted vlan frame 0: transmitted frame had length/type field of 0x8100. 1: transmitted frame did not have a length/type field of 0x8100. bit 2: bckpres: back pressure applied 0: back pressure was not applied during transmission. 1: back pressure was applied during transmission. bit 1: txpf: transmitted pause frame 0: transmitted frame was not a pause control frame. 1: transmitted frame was a valid pause control frame. bit 0: txcf: transmitted control frame 0: transmitted frame was not a control frame. 1: transmitted frame was a control frame. r/w r/w r/w r/w r r r r reset value ? ? ? ? txvlan bckpres txpf txcf 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x5c note: this register contains bits 47? 40 of the transmit status vector. bits 7?0: txsta5: total bytes transmitted high byte the most significant 8-bits of the total number of bytes transmitted on the wire, including all bytes from collided attempts. rrrrrrrrreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x5d
cp2200/1 rev. 1.0 55 register 29. txsta4: transmit status vector 4 register 30. txsta3: transmit status vector 3 note: this register contains bits 40-32 of the transmit status vector. bits 7-0: txsta4: total bytes transmitted low byte the least significant 8-bits of the total number of bytes transmitted on the wire, including all bytes from collided attempts. rrrrrrrrreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x5e note: this register contains bits 31? 24 of the transmit status vector. bit 7: txurun: transmit under-run 0: transmit under-run did not occur. 1: packet aborted due to data under-run condition. bit 6: txjumbo: jumbo packet detected 0: transmitted packet was not oversized. 1: packet aborted due to its excessive size. bit 5: txltcl: late collision detected 0: late collision was not detected. 1: packet aborted due to the detection of a collision after the 51.2 us collision window. bit 4: txexcl: excessive collisions detected 0: number of collisions on tr ansmission was less than 16. 1: packet aborted due to detection of 16 or more collisions. bit 3: txexde: excessive delay detected 0: packet was transmitted without an excessive del ay (greater than 2.42 ms). please check other flags for information. 1: packet was aborted due to an excessive delay (greater than 2.42 ms). bit 2: txde: delay detected 0: packet was transmitted with no delay or was a borted. please check other flags for information. 1: packet was transmitted, but had some delay (less than 2.4 ms). bit 1: txbcast: transmitted broadcast packet 0: transmitted packet did not have a broadcast destination address. 1: transmitted packet had a broadcast destination address. bit 0: txmcast: transmitted multicast packet 0: transmitted packet did not have a multicast destination address. 1: transmit packet had a multicast destination address. rrrrrrrrreset value txurun txjumbo txltcl txexcl txexde txde txbcast txmcast 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x5f
cp2200/1 56 rev. 1.0 register 31. txsta2: transmit status vector 2 register 32. txsta1: transmit status vector 1 note: this register contains bits 23? 16 of the transmit status vector. bit 7: txok: transmit successful 0: transmission was aborted. 1: transmission was successful. bit 6: txloor: type field detected 0: last packet?s type/length field was used as a length. 1: last packet?s type/length field was used as a type. bit 5: txlcerr: length check error 0: last packet?s length field matched the actual frame length. 1: last packet?s length field did not match the actual frame length. bit 4: txcrcer: crc error 0: last packet?s crc matched the internally generated crc. 1: last packet?s crc did not ma tch the internally generated crc. bits 3?0: txcol3-0: tr ansmit collision count number of collisions enco untered during transmission of the last packet. note: this bit field does not overflow and will remain at 1111b (15 collisions) if 15 or more collisions are encountered. rrrrrrrrreset value txok txtype txlcerr txcrcer txcol3 txcol2 txcol1 txcol0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x60 note: this register contains bits 15?8 of the transmit status vector. bits 7?0: txsta1: transmit byte count high byte the most significant 8-bits of the number of byte s in the last transmitted frame. does not include bytes transmitted due to collided attempts. rrrrrrrrreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x61
cp2200/1 rev. 1.0 57 register 33. txsta0: transmit status vector 0 note: this register contains bits 15?8 of the transmit status vector. bits 7?0: txsta0: transmit byte count low byte the least significant 8-bits of the number of byte s in the last transmitted frame. does not include bytes transmitted due to collided attempts. rrrrrrrrreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x62
cp2200/1 58 rev. 1.0 12. receive interface 12.1. overview the cp2200/1 has a 4k circular receive fifo buffer and an 8 entry translation look-aside buffer (tlb) capable of storing up to 8 packets at a time. each tlb entry holds the starting address, length, and other information about a single received packet. once a packet is received, the ho st microcontroller is notifie d using the interrupt request pin. the host microcontroller may then copy the contents of the packet to its local memory through the host interface or skip the packet by writing ?1? to rxskip (rxcn.1). skip ped packets remain in memory but will be overwritten as new packets arrive. the receive interface has an advanced receive filter and hash table to prevent unwanted packets from reaching the receive buffer. for all packet types not supported by the re ceive filter, the cp2200/1 allows the host microcontroller complete random access to the receive buffer. the host microcontroller can check specific bytes in the packet to determine whether or not to copy the packet. . figure 17. receive interface block diagram 12.2. reading a packet usin g the autoread interface once reset initialization is complete (section 6.2 on page 18) and the receiv e buffer, filter, and hash table (section 12.4) are initialized, the cp2200/1 is ready to receive ethernet packets. after receiving notification of a new packet, the following procedure can be used to read the packet: step 1: read rxvalid (cpinfoh.7) and rxok (cpinf ol.7) to check if the cu rrent packet was received correctly. the host processor may optionally use the packet starting address cpaddr to read specific bytes in the packet and determine whether to copy or skip the current packet. the random access method described in section 7.1 on p age 23 can be used to access the buffer. step 2: if rxvalid or rxok is 0, or to sk ip the packet, write a ?1? to rxskip (rxcn.1). if rxvalid and rxok are 1, read the length of the current packet from cplenh:cplenl. step 3: read the entire packet, one byte at a time, by reading rxautord. step 4: if the entire packet was r ead, write a ?1? to rxclrv (rxcn.2). if there are any unread bytes re maining in the current buffer, write a ?1? to rxskip (rxcn.1). 12.3. timing and buffer overflow considerations for 10 base-t ethernet, a minimum-sized packet of 64 by tes is received in 51.2 us. the maximum number of packets that can be held by the receive buffer is eight. to ensure that pointer corruption does not occur, software should disable packet reception (rxinh = 1) after the seventh packet has arri ved in the receive buffer. if the ability to service the packet received interrupt is longer than 51.2us, then software should use the random access method to retrieve data from the receive buffer. the random access method described in section 7.1 on page 23. 4 kb receive buffer with 8-entry tlb programmable receive filter and hash table host interface registers autoread interface: autoread data register packet skip bit current packet: packet address packet length packet information
cp2200/1 rev. 1.0 59 note: the value of cpaddrh:cpaddrl may be invalid if an overflow event occurs. after an overflow, the fifoheadh:fifo- headl pointer should be used to determine the starting address of the current packet. cplen will always remain valid even after an overflow event. note: if the receive fifo full interr upt is triggered, the interrupt flag must be cleared to re-enable packet reception. the receive fifo full interrupt is triggered based on the size of packets or on the number of packets. if triggered based on the number of packets, then pointer corruption has occurred. 12.4. initializing the receive buffer, filter and hash table after a device reset, the receive buffer is empty and the filter is configured to accept broadcast packets and multicast packets matching a hash value of 0x0400. th is hash value allows pause control packets to pass through the receive filter. the receive buffer does not require any additional initializat ion. the receive filter can be configured to accept or ignore broadcast packets, multicast packets, runt pack ets (ethernet frame smaller than 64 bytes), and packets with a crc error. the receive filter is configured using the rxfilt register. the device can be configured to acce pt broadcast packets and packets addr essed to the controller?s mac address without using the hash table. if multicast packets need to be accepted, then the hash table can be programmed to accept packets addressed to specific address ranges. the cp2200/1 implements a 16-bit hash table to represent all possible addresses in the 64-bit address space. each of the possible 65536 possible values for the hash table represent a range of mac addresses. if all 16 bits are set to ?1?, all multicast addresses will be accepted. if all 16-bit s are set to ?0?, then a ll multicast addresses will be rejected.the following procedure can be used to determine which bits to set for a specific address: step 1: perform a 32-bit crc on the 6-bytes of the addre ss using 0xc704dd7b as the polynomial. step 2: record the least significant 4 bits of the crc result (hash index). step 3: the hash index dete rmines the bit that should be set in the hash table that will allow the address to be received. for example, if the least significant 4- bits of the crc result are 101b (5d), then setting bit 5 of the 16-bit hash table will allow all mac addresses whose crc result is 5d to be accepted.
cp2200/1 60 rev. 1.0 12.5. receive status and control registers the cp2200/1 receive interface is controlled and managed through the registers in table 16. the current packet registers provide information about the next packet to be unloaded from the receive buffer (the oldest packet received). table 16. receive status and control register summary register long name address description rxcn receive interface control 0x11 contains rece ive interface control bi ts such as rxskip, rxclrv, rxrst, and rxinh. rxsta receive interface status 0x12 indicates when the receive interface is busy receiving a frame and when the current packet has been completely read from the buffer. rxautord receive autoread 0x01 provides an efficient method of reading entire packets sequentially from the receive buffer. rxfilt receive filter configuration 0x10 specifies the type of packets can pass through the receive filter. rxhashh rxhashl multicast hash table 0x0e 0x0f 16-bit hash table used to filter multicast packets. cpinfoh cpinfol current packet information 0x1d 0x1e specifies information about the current packet such as broadcast/multicast, crc errors, etc. cplenh cplenl current packet length 0x1f 0x20 specifies the length of the current packet in the receive buffer (in bytes). cpaddrh cpaddrl current packet address 0x21 0x22 specifies the starting address of the current packet in the receive buffer.
cp2200/1 rev. 1.0 61 register 34. rxcn: recei ve interface control register 35. rxsta: receive interface status bits 7?4: unused. read = 0000b, write = don?t care. bit 3: rxinh: receive inhibit setting this bit to ?1? temporarily inhibits new packet reception. if a packet is currently being received, reception will continue unt il the packet is received. once set, this bit must be cleared to ?0? by software to resume packet reception. bit 2: rxclrv: valid bit clear writing a ?1? to this bit clears the valid bit of the current packet, freeing up the buffer for new packets. this action should only be started after all bytes of the current packet have been read (cpend = 1). if the packet is not completely read, rxskip should be used to discard the remaining bytes. bit 1: rxskip: skip current packet writing a ?1? to this bit updates discards the current packet by clearing its valid bit and advances the autoread buffer pointer to the beginning of the next packet. bit 0: rxclear: receive buffer clear writing a ?1? to this bit discards all packets in the receive buffer and resets all buffer pointers and valid bits to zero. note: any packets currently in the buffer will remain in me mory, however, all infor- mation such as the starting addre ss and length of each packet will be lost. any new packets that arrive will overwrite the existing data. r/w r/w r/w r/w r/w w w w reset value ? ? ? ? rxinh rxclrv rxskip rxclear 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x11 bits 7?2: unused. read = 000000b, write = don?t care. bit 1: cpend: current packet end reached this bit is automatically cleared by hardware when the valid bit for the current packet is cleared (see rxclrv description) or the current packet is discarded (see rxskip description). 0: the last byte of the current packet has not been read using the autoread interface. 1: the last byte of the current packet has been read using the autoread interface. bit 0: rxbusy: receiving packet 0: receive interface is idle. 1: receive interface is cu rrently receiving a packet. r/wr/wr/wr/wr/wr/w r rreset value ? ? ? ? ? ? cpend rxbusy 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x12
cp2200/1 62 rev. 1.0 register 36. rxautord: receive autoread data register register 37. rxfilt: recei ve filter c onfiguration register 38. rxhashh: multi cast hash table high byte bits 7?0: rxautord: receive autoread data register reads from this register read a single byte from the receive buffer and adjust the receive buffer pointer rxfifohead accordingly. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x01 bits 7?4: unused. read = 0000b, write = don?t care. bit 3: ignrunt: ignore runt packets 0: runt packets are not ignored. 1: runt packets are ignored. bit 2: ignerr: ignore fcs error packets 0: packets with fcs error are not ignored. 1: packets with fcs error are ignored. bit 1: ignbcst: ignore broadcast packets 0: broadcast packets are not ignored. 1: broadcast packets are ignored. bit 0: ignmcst: ignore multicast packets 0: multicast packets are not ignored. 1: multicast packets are ignored. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ignrunt ignerr ignbcst ignmcst 00001100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x10 bits 7?0: rxhashh: multicast hash table high byte high byte of 16-bit multicast hash table. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x0e
cp2200/1 rev. 1.0 63 register 39. rxhashl: multi cast hash table low byte register 40. cpinfoh: current packet information high byte bits 7?0: rxhashl: multicast hash table low byte low byte of 16-bit multicast hash table. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x0f bit 7: rxvalid: current packet valid 0: the current packet tlb slot is empty. 1: there is a packet in the current packet tlb slot. bit 6: rxvlan: vlan type detected 0: vlan tagged frame not detected. 1: vlan tagged frame detected. bit 5: rxunsup: unsupp orted control frame 0: unsupported control frame not detected. 1: unsupported control frame detected. bit 4: rxpcf: pause control frame 0: pause control frame not detected. 1: pause control frame detected. bit 3: rxcf: control frame 0: control frame not detected. 1: control frame detected. bit 2: rxadata: additional data received 0: normal operation. 1: 1 to 7 additional bits of data received following receipt of the packet. bit 1: bcast: broadcast packet 0: current packet is not a broadcast packet. 1: current packet is a broadcast packet. bit 0: mcast: multicast packet 0: current packet is no t a multicast packet. 1: current packet is a multicast packet. rrrrrrrrreset value rxvalid rxvlan rxucf rxpcf rxcf rxadata bcast mcast 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x1d
cp2200/1 64 rev. 1.0 register 41. cpinfol: current packet information low byte register 42. cplenh: curren t packet length high byte register 43. cplenl: current packet length low byte bit 7: rxok: receive ok 0: receive not ok. 1: receive ok. bit 6: length: length/type field detection 0: the length/type field of the current packet contains the packet length. 1: the length/type field of the current packet contains the packet type. bit 5: lenerr: length check error 0: no errors detected in length field. 1: the length field does not match actual packet length. bit 4: crcerr: crc error 0: crc check passed. 1: crc check failed. bits 3?2: reserved: read = varies. bit 1: rxlen: receive length 0: normal operation. 1: the data received is not long enough to form a valid packet. bit 0: rxdrop: packet dropped 0: normal operation. 1: a packet has been dropped. rrrrrrrrreset value rxok length lenerr crcerr reserved reserved rxlen rxdrop 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x1e bits 7?0: cplenh: current packet length high byte high byte of the current packet length. rrrrrrrrreset value ????????00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x1f bits 7?0: cplenl: current packet length low byte low byte of the current packet length. rrrrrrrrreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x20
cp2200/1 rev. 1.0 65 register 44. cpaddrh: current packet address high byte register 45. cpaddrl: curre nt packet a ddress low byte note: the contents of this register are invalid following a buffer overflow event. bits 7?0: cpaddrh: current packet address high byte high byte of the current packet starting address in the receive fifo buffer. rrrrrrrrreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x21 note: the contents of this register are inva lid following a buffer overflow event. bits 7?0: cpaddrl: current packet address low byte low byte of the current packet starting address in the receive fifo buffer. rrrrrrrrreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x22
cp2200/1 66 rev. 1.0 12.6. advanced receive buffer operation receive buffer operation is automatically handled by ha rdware and does not require any assistance from the host processor. note: the information in this section is provided for reference purposes only and will typically not be used except when debugging a problem and a dditional control over the receive buffer is required. figure 18 shows a detailed block diagram of the receive buffer. as packets arrive and pass through the receive filter, they are added to the circular re ceive buffer at the address pointed to by the tail pointer. th e fifo tail pointer is incremented after each byte is received. as soon as a new packet arrives, the receive buffer controller searches for an unused tlb slot to store data about the received pa cket. if an unused tlb slot is found, it is claimed and assigned to the packet currently being re ceived by setting the slot?s valid bit to ?1?. a packet re ceived interrupt will be generated after the entire packet is copied to the buffer. if all 8 slots are full (valid bits for all slots are set to ?1?) , then the packet will be droppe d and a receive fifo full interrupt will be generated. each tlb slot holds information about its assigned packet such as starting address in the buffer, length, and information about the packet such as the type (broadcast, multicast, unicast) and any er rors that occurred during reception (crc error, incomplete packet, etc.). the receive buffer controller rotates through the tlb slots in a circular fashion. for debugging purposes, the host pr ocessor may access any tlb slot using the tlb registers listed in table 17. figure 18. receive buffer block diagram the oldest packet received starts at the address pointed to by the fifo head pointer. this packet (packet #1 in figure 18) will be referred to as the current packet. the fifo head point er is used by the autoread interface to read data from the current packet. as data is read using the autoread interface, the fifo head pointer is incremented until the entire packet is read out. once the pack et is read out, the host pr ocessor must clear the valid bit of the packet by writing a ?1? to rxclrv (rxcn.2). if the host processor chooses not to read the entire packet, the valid bit should be cleared (and unread data skipped) by writing a ?1? to rxskip (rxcn.1). a copy of the tlb slot associated with the current packet is always available by reading the ctlb registers listed in table 16. the same information can be obtained by reading cptlb to determine the current tlb slot, then directly accessing the slot using the registers in table 17. 0 1 1 1 0 0 0 0 fifo head pointer fifo tail pointer packet #1 packet #2 packet #3 4 kb receive buffer tlb0 tlb1 tlb2 tlb3 tlb4 tlb5 tlb6 tlb7 translation look-aside buffer (8-entry circular or random access) current packet address, length, and information. valid bit cpinfo/ cplen/ cpaddr copy of current tlb cptlb current tlb entry number (e.g. 0 for tlb0) rxautord autoread interface automatically manages read pointers. tlb entries are typically not accessed by the host.
cp2200/1 rev. 1.0 67 the receive fifo full interrupt will be generated once a ll free space in the buffer is used or all tlb slots are filled. the host processor should read the rxfifosta register to determine the cause of the interrupt. to receive additional packets after the buffer is filled, packets must be removed from the buf fer by reading them out or discarding them. packets can be discarded one at a time or all at once by writing ?1? to rxclear (rxcn.0). 12.7. receive buffer advanced status and control registers the receive buffer is controlled and managed through the registers in table 17. these registers are not commonly accessed by the host processor except for debug purposes. register 46. cptlb: current packet tlb number table 17. receive status and control register summary register long name address description cptlb current packet tlb number 0x1a specif ies the tlb number (0?7) associated with the current packet. tlbvalid tlb valid indicator 0x1c indicates which tlbs current ly have valid pack- ets. tlbninfoh tlbninfol tlbn packet information mu ltiple specifies information about the packet associ- ated with tlbn (n = 0?7). tlblenh tlblenl tlbn packet length multiple specifies the length of the packet associated with tlbn (n = 0?7). tlbnaddrh tlbnaddrl tlbn packet address multiple specifies the starting address of the packet associated with tlbn (n = 0?7). rxfifotailh rxfifotaill receive fifo buffer tail pointer 0x15 0x16 points to the byte follo wing the last valid byte. this is where new packets are added. rxfifoheadh rxfifoheadl receive fifo buffer head pointer 0x17 0x18 points to the beginning of the current packet and is incremented wit h each auto read. rxfifosta receive fifo buffer status 0x5b indi cates the cause of the receive fifo buffer full interrupt. bits 7?3: unused. read = 00000b; write = don?t care. bits 2?0: cptlb[2:0]: current packet tlb number the tlb number (0?7) of the tlb slot associated with the current packet. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? cptlb 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x1a
cp2200/1 68 rev. 1.0 register 47. tlbvalid: tlb valid indicator register 48. tlbninfoh: tlbn information high byte bits 7?0: tlbvalid: tlb valid indicator displays the valid bits for the eight tlb slots in a single byte. note: this register may be used to clear multiple va lid bits simultaneously. for all writes, bits with a value of ?0? will cause the associ ated valid bit to be cleared, a nd bits with a value of ?1? will be ignored. for exam ple, writing 0xfe to this register will clear the valid bit for tlb0. r/w r/w r/w r/w r/w r/w r/w r/w reset value val7 val6 val5 val4 val3 val2 val1 val0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x1c address: tlb0infoh: 0x23; tlb1infoh: 0x 29; tlb2infoh: 0x2f ; tlb3infoh: 0x35; tlb4infoh: 0x3b; tlb5infoh: 0x41; tlb6infoh: 0x47; tlb7infoh: 0x4d bit 7: reserved. read = varies; bit 6: rxvlan: vlan type detected 0: vlan tagged frame not detected. 1: vlan tagged frame detected. bit 5: rxunsup: unsupp orted control frame 0: unsupported control frame not detected. 1: unsupported control frame detected. bit 4: rxpcf: pause control frame 0: pause control frame not detected. 1: pause control frame detected. bit 3: rxcf: control frame 0: control frame not detected. 1: control frame detected. bit 2: rxadata: additional data received 0: normal operation. 1: 1 to 7 additional bits of data received following receipt of the packet. bit 1: bcast: broadcast packet 0: packet is not a broadcast packet. 1: packet is a broadcast packet. bit 0: mcast: multicast packet 0: packet is not a multicast packet. 1: packet is a multicast packet. rrrrrrrrreset value reserved rxvlan rxucf rxpcf rxc f rxadata bcast mcast 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
cp2200/1 rev. 1.0 69 register 49. tlbninfol: tlbn information low byte register 50. tlbnlenh: tlbn packet length high byte address: tlb0infoh: 0x24; tlb1infoh: 0x2a; tlb2infoh: 0x30; tlb3infoh: 0x36; tlb4infoh: 0x3c; tlb5infoh: 0x42; tlb6infoh: 0x48; tlb7infoh: 0x4e bit 7: rxok: receive ok 0: receive not ok. 1: receive ok. bit 6: length: length/type field detection 0: the length/type field of the current packet contains the packet length. 1: the length/type field of the current packet contains the packet type. bit 5: lenerr: length check error 0: no errors detected in length field. 1: the length field does not match actual packet length. bit 4: crcerr: crc error 0: crc check passed. 1: crc check failed. bits 3?2: reserved: read = varies. bit 1: rxlen: receive length 0: normal operation. 1: the data received is not long enough to form a valid packet. bit 0: rxdrop: packet dropped 0: normal operation. 1: a packet has been dropped. rrrrrrrrreset value rxok length lenerr crcerr reserved reserved rxlen rxdrop 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: tlb0lenh: 0x25; tlb1lenh: 0x2b; tlb2lenh: 0x31; tlb3lenh: 0x37; tlb4lenh: 0x3d; tlb5lenh: 0x43; tlb6lenh: 0x49; tlb7lenh: 0x4f bits 7?0: tlbnlenh: tlbn packet length high byte high byte of the packet length for the packet associated with tlbn. rrrrrrrrreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
cp2200/1 70 rev. 1.0 register 51. tlbnlenl: tlbn packet length low byte register 52. tlbnaddrh: tlbn packet address high byte register 53. tlbnaddrl: tlbn packet address low byte address: tlb0lenh: 0x26; tlb1lenh: 0x2c; tlb2lenh: 0x32; tlb3lenh: 0x38; tlb4lenh: 0x3e; tlb5lenh: 0x44; tlb6lenh: 0x4a; tlb7lenh: 0x50 bits 7?0: tlbnlenl: tlbn packet length low byte low byte of the packet length for the packet associated with tlbn. rrrrrrrrreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 note: the contents of this register are invalid following a buffer overflow event. address: tlb0addrh: 0x27; tlb1addrh: 0x2d; tlb2addrh: 0x33; tlb3addrh: 0x39; tlb4addrh: 0x3f; tlb5addrh: 0x45 ; tlb6addrh: 0x4b; tlb7addrh: 0x51 bits 7?0: tlbnaddrh: tlbn packet address high byte high byte of the packet starting address for the packet associated with tlbn. rrrrrrrrreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 note: the contents of this register are invalid following a buffer overflow event. address: tlb0addrh: 0x28; tlb1addrh: 0x2e; tlb2addrh: 0x34; tlb3addrh: 0x3a; tlb4addrh: 0x40; tlb5addrh: 0x46; tlb6addrh: 0x4c; tlb7addrh: 0x52 bits 7?0: tlbnaddrl: tlbn packet address low byte low byte of the packet starting address for the packet associated with tlbn. rrrrrrrrreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
cp2200/1 rev. 1.0 71 register 54. rxfifoheadh: receive fifo head pointer high byte register 55. rxfifoheadl: receive fifo head pointer low byte register 56. rxfifotailh: receive fifo tail pointer high byte register 57. rxfifotaill: receive fifo tail pointer low byte bits 7?0: rxfifoheadh: receive fifo head pointer high byte high byte of the receive fifo buffer head pointer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x17 bits 7?0: rxfifoheadl: receiv e fifo head pointer low byte low byte of the receive fifo buffer head pointer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x18 bits 7?0: rxfifotailh: receiv e fifo tail pointer high byte high byte of the receive fifo buffer tail pointer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x15 bits 7?0: rxfifotaill: receive fifo tail pointer low byte low byte of the receive fifo buffer tail pointer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x16
cp2200/1 72 rev. 1.0 register 58. rxfifosta: rece ive fifo status register this register is set by hardware and is valid after an rx fifo full interrupt is generated or if tlbvalid equals 0xff. bits 7?2: unused. read = 000000b, write = don?t care. bits 1?0: fifosta[1:0]: receive fifo status 00: initial value? no information. 01: the last packet successfully received used all available free space in the buffer. 10: the last packet successfully received was th e 8th packet in the receive buffer. there is free space remaining in the receive buffer; however, the maximum number of packets in the buffer has been reached. any future packe ts received will cause overflow. note: receiving an unsuccessful 9th packet will cause overflow. 11: the last packet successfully received was the ei ghth packet in the receive buffer and used all available free space in the buffer. r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? ? fifosta1 fifosta0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x5b
cp2200/1 rev. 1.0 73 13. flash memory the cp2200/1 has 8 kb of on-chip non-volatile flash memory fully accessible by the host processor. the last six bytes of this memory space (addresses 0x1ffa to 0x 1fff) are factory preprogrammed and contain a unique 48- bit mac address (individual a ddress) registered with the i eee registration authority. th e most significant byte of the mac address is at 0x1ffa, and the least significant byte is at 0x1fff. the last page of flash containing the mac address is erasable, and the user should exercise caution to prevent erasing the mac address. 13.1. programming the flash memory the flash memory can be programmed one byte at a time th rough the parallel host interface. once cleared to a logic 0, a flash bit must be erased to set it back to logic 1. a flash bit may always be changed from logic 1 to logic 0, as long as flash bytes are only written once be tween erase cycles. flash eras e operations erase an entire 512 byte sector at a time. fl ash write and erase operations are automati cally timed by hardware and do not affect the parallel host interface. after initiating a flash write or erase operation, the host cpu can continue to access the cp2200/1 through the parallel host interface while the flash operation is taking place. the host is notified with an interrupt request when the flash write or erase operation is complete. refer to table 18 for complete flash memory electrical characteristics includ ing typical write and erase cycle times. the flash memory can be writ ten and erased using the flash addrh:flashaddrl, flashdata, and flasherase registers. once a flash o peration is initiated, the status can be moni tored using the flashsta register, or the host can wait for notification by the interrupt signal. 13.1.1. flash lock and key protection the flash memory is protected from errant write and eras e operations by a lock and key function. flash reads are unrestricted. the flash lo ck and key register (fl ashkey) must be written wit h the correct key codes, in sequence, before each flash write or er ase operation. if a flash write or erase operation is attempted without first writing the correc t key codes to the flashkey regist er, flash cannot be written or erased until the next reset. after programming flash, the cp2200/1 should be reset in order to protect the device from errant flash operations. the key codes for unlocking the cp2200/1 are 0xa5 and 0x f1. these codes must be written in sequence to the flashkey register prior to each flash write or erase operation. note: to ensure the integrity of flash contents, the on-chip v dd monitor should not be disabled while the flash memory is unlocked. 13.1.2. flash erase procedure step 1: write 0xa5 followed by 0xf1 to flashkey. step 2: set flashaddrh:flashaddr l to any address within the 512-byte page to be erased. step 3: write the value 0x01 to flasherase. step 4: check flashsta to determine when the flash operation is complete. the flash write/erase completed interrupt can also be use to determine when the operation completes. 13.1.3. flash write procedure step 1: write 0xa5 followed by 0xf1 to flashkey. step 2: if the byte to be written is not 0x ff, then erase the page containing the byte. step 3: set flashaddrh:flashaddrl to the address of the byte to be written. step 4: write the value to be written to the flashdata register. step 5: check flashsta to determine when the flash operation is complete. the flash write/erase completed interrupt can also be used to determine when the operation is complete.
cp2200/1 74 rev. 1.0 13.2. reading the flash memory flash reads occur much faster than flash write or erase operations and are completed within the minimum read strobe time specified by the para llel host interface. flash is r ead using the flashaddrh:flashaddrl, flashdata, and flashautord register s. the flashautord register provides an efficient method of accessing sequential data in flash by automatically in crementing the flash address pointer after each read. 13.2.1. flash read procedure step 1: set flashaddrh:flashaddrl to th e address of the by te to be read. step 2: read the value of the byte from flashdata. 13.2.2. multiple byte flash read procedure step 1: set flashaddrh:flashaddrl to the ad dress of the first byte to be read. step 2: for each byte, read the value from flashautord. table 18. flash electrical characteristics v dd = 3.1 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units flash size 8192 ? ? bytes endurance 20k 100k ? erase/ write erase cycle time ? 11 ? ms write cycle time 40 55 70 s
cp2200/1 rev. 1.0 75 13.3. flash access registers the cp2200 flash is accessed through the registers in table 17. see the register tables following table 17 for detailed register descriptions register 59. flashsta: fl ash status register table 19. flash access register summary register long name address description flashsta flash status 0x7b used to deter mine the status of a flash write or erase operation. flashkey flash lock and key 0x67 write-only register allowing the host to unlock the flash for writing or erasing. flashaddrh flashaddrl flash address register high and low bytes 0x69 0x68 16-bit address used for flash operations. flashdata flash read/write data register 0x06 data register used for writing or reading a single byte of flash. flashautord flash autoread data register 0x05 data register used for reading a block of sequential data stored in flash. each read from this register increments the flash address register by 1. flasherase flash erase 0x6a initia tes a flash erase operation. note: to determine when a flash operation completes, the flbusy bit should be polled or software should wait for the flash write/erase operation complete interrupt to occur. bits 7?4: unused. read = 0000b, write = don?t care. bit 3: flbusy: flash busy indicator this bit indicates when a flash write or erase operation is in progress. 0: flash is idle. 1: flash write/erase operati on is currently in progress. bit 2: reserved. bit 1: flwrite: flash write 0: the last flash operation completed was not a flash write. 1: the last flash operation completed was a flash write. bit 0: flerase: flash erase 0: the last flash operation completed was not a flash erase. 1: the last flash operation completed was a flash erase. r/w r/w r/w r/w r r r r reset value ? ? ? ? flbusy reserved flwrite flerase 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x7b
cp2200/1 76 rev. 1.0 register 60. flashkey: flash lock and key register register 61. flashaddrh: flash address register high byte register 62. flashaddrl: flash address register low byte bits 7-0: flkey: flash lock and key register this register must be written to unlock the flash fo r writing or erasing. to un lock the flash, first write 0xa5 and then 0xf1 to this register. the v dd monitor should not be disabled while the flash is unlocked. the device must be unlocked prior to each flash write/erase operation. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x67 bits7?0: flashaddrh: flash address register high byte holds the most significant eight bits of the target flash address. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x69 bits7?0: flashaddrl: flash address register low byte holds the least significant eight bits of the target flash address. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x68
cp2200/1 rev. 1.0 77 register 63. flashdata: flash read/write data register register 64. flashautord: flash autoread data register register 65. flasherase: flash erase register bits7?0: flashdata: flash read/write data register read: value of the flash byte at the loca tion specified by flashaddrh:flashaddrl. write: initiates a flash write operation to the flash byte at th e address in flashaddrh:flashaddrl. the flash memory must be unlocked, and the target flash byte should have a value of 0xff (value of erased flash). r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x06 bits7?0: flashautord: flash autoread data register reads from this register return the value of the flash byte at the location specified by the flash address register. the flash address register is automatically incremented by 1 after the read. rrrrrrrrreset value 00000000 bit7 bit6 bit5 bit4 b bit2 bit1 bit0 address: 0x05 bits 7?2: unused. read = 000000b, write = don?t care. bit 1: reserved. must write 0b. bit 0: flego: flash erase start. writing a ?1? to this bit initiates a flash erase oper ation on the 512-byte page of flash containing the flash byte at the location specified in the flas h address register. the flash memory must be unlocked prior to starting a flash erase operation. r/w r/w r/w r/w r/w r/w r/w r/w reset value ??????reservedflego00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x6a
cp2200/1 78 rev. 1.0 14. media access controller (mac) the cp2200/1 has an ieee 802.3 complia nt ethernet media access cont roller (mac). the mac can be configured to automatically pad short frames (full du plex mode only), append crc, and perform frame length checking. a loopback mode separate from phy loopbac k is also provided for system debugging. the mac is configured through nine indirect 16-bit registers summarized in table 20. 14.1. initializing the mac mac initialization occurs afte r the physical layer initializat ion and typically occurs once after each reset or auto- negotiation complete interrup t. most mac indirect registers can be left at their reset values. see ?6.2. reset initialization? on page 18 for the comp lete reset initialization procedure. the following are the steps required to initialize the mac: step 1: determine if th e physical layer is set to full-duplex or ha lf-duplex. the mac must be set to the same duplex mode as the physical layer before sending or receiving any packets. step 2: write 0x40b3 (full-duplex) or 0x4012 (half-duplex) to maccf. the appropriate bits in this register may also be set or cleared to change padding options or mac behavior. step 3: write 0x0015 (full-duplex) or 0x0012 (half-duplex) to ipgt . step 4: write 0x0c12 to ipgr . step 5: write 0x05ee to maxlen . step 6: program the 48-bit ethernet mac address by writing to macad0:macad1:macad2. step 7: write 0x0001 to maccn to enable reception. if loopback mode or flow control is desired, set the appropriate bits to enable these functions. 14.2. accessing the i ndirect mac registers the indirect mac registers are accessed through fo ur direct mapped registers: macaddr, macdatah, macdatal, and macrw. the mac registers can be accessed using the following procedure: step 1: write the address of the indirect register to macaddr. step 2: if writing a value to the indirect regi ster, write a 16-bit value to macdatah:macdatal. step 3: write any value to macrw to transfer the contents of macdatah:macdatal to the indirect register. step 4: perform a read on macrw to transfer the contents of the indirect register to macdatah:macdatal. the macdatah and macdatal registers may now be directly read to determine the contents of the indirect register.
cp2200/1 rev. 1.0 79 register 66. macaddr: ma c indirect address register 67. macdatah: mac data high byte register 68. macdatal: mac data low byte register 69. macrw: mac read/write initiate bits 7?0: macaddr: mac indirect address indirect mac register address targeted by reads/writes to macrw. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x0a bits 7?0: mac data high byte holds the most significant 8-bits of data read or written to an indirect mac register. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x0b bits 7?0: mac data low byte holds the least significant 8-bits of data read or written to an indirect mac register. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x0c bits 7?0: mac read/write initiate initiates a read or write to the indirect mac register at the address stored in macaddr. write: the contents of macdatah:macdatal ar e transferred to the target mac register. read: the contents of the target mac register are transferred to macdatah:macdatal. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x0d
cp2200/1 80 rev. 1.0 14.3. indirect mac register descriptions the mac is configured through nine indirect 16-bit regist ers listed in table 20. see the figures following table 20 for detailed register descriptions. table 20. indirect mac register summary register long name address description maccn mac control 0x00 used to enable reception and other options. maccf mac configuration 0x01 used to configure padding options and other settings. ipgt back-to-back interpacket delay 0x02 set s the back-to-back interpacket delay. ipgr non-back-to-back interpacket delay 0x03 sets the non-back-to-back interpacket delay. cwmaxr collision window and maximum retransmit 0x04 sets the collision wi ndow size and the maxi- mum number of retransmits allowed. maxlen maximum frame length 0x05 sets the maximum receive frame length. macad0 macad1 macad2 mac address 0x10 0x11 0x12 sets the mac address of the local device.
cp2200/1 rev. 1.0 81 indirect register 1. macc n: mac control register bit 15: reserved. read = varies; must write 0b. bit 14: randrst: random number generator reset writing a ?1? to this bit resets the random number generator within the transmit function. bits 13?5:reserved. read = varies; must write 000000000b. bit 4: loopbck: loopback mode enable bit note: mac loopback mode is independent of the physical layer loopback mode. 0: normal operation. 1: mac transmit data is internally looped back as mac receive data. bit 3: txpause: tx flow control enable bit (full-duplex only) 0: pause control frames are blocked. 1: pause control frames are allowed to pass through the mac. bit 2: rxpause: rx flow control enable bit (full-duplex only) 0: pause control frames received from the physical layer are ignored. 1: pause control frames received from the physical layer are acted upon. bit 1: reserved. read = 0; must write 0b. bit 0: rcven: receive enable 0: the mac blocks control frames from reaching the receive interface. the mac blocks all received packets from the receive interface. 1: the mac allows received packets to reach the receive interface. r/w r/w r/w r/w r/w r/w r/w r/w reserved randrst reserved bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 r/w r/w r/w r/w r/w r/w r/w r/w default value reserved loopbck txpause rx pause reserved rcven 0x8000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 macaddr: 0x00
cp2200/1 82 rev. 1.0 indirect register 2. maccf: mac configuration register bit 15: reserved. read = 0b; must write 0b. bit 14: abortd: abort disable bit 0: mac will abort when excessive delay is dete cted and update the tr ansmit status vector. 1: mac will attempt to transmit indef initely as specif ied in ieee 802.3. bit 13: ebbpd: exponential backoff after back pr essure disable bit (half-duplex only) 0: after incidentally causing a collision during back pressure, the mac will use the exponential backoff algorithm as sp ecified in ieee 802.3. 1: after incidentally causing a collision during back pressure, the mac will immediately transmit without using the exponential backoff algorithm. bit 12: ebd: exponential backoff disable (half-duplex only) 0: mac will use the expon ential backoff algorithm as specified in ieee 802.3. 1: mac will immediately retr ansmit following a collision. bits 11?10:reserved. read = 00b; write = don?t care. bit 9: rlpre: reject long preamble 0: mac allows any length preamb le as specified in ieee 802.3. 1: mac rejects packets with a preamble greater than 12 bytes in length. bit 8: purepre: pure preamble enforcement 0: no preamble checking is performed. 1: mac will verify the content of t he preamble to ensure it contains 0x55 and is error-free. packets with an invalid pream ble will be rejected. bit 7?6: padmd[1:0]: pad mode note: this bit field is ignored if paden is cleare d to ?0?. see table 21 for a complete description. bit 5: paden: pad enable bit (must be set to 0 in half-duplex operation) note: see table 21 for a complete description. bit 4: crcen: crc enable bit note: this bit must be set to ?1? if padding is enabled. 0: crc will not be appended. frames pr esented to the mac must contain crc. 1: crc will be appended. r/w r/w r/w r/w r/w r/w r/w r/w reserved abortd ebbpd ebd reserved rlpre purepre bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 r/w r/w r/w r/w r/w r/w r/w r/w default value padmd1 padmd0 paden crcen pheader reserved lenchk flldplx 0x0000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 macaddr: 0x01
cp2200/1 rev. 1.0 83 indirect register 2. maccf: mac c onfiguration register (continued) bit 3: pheader: proprietar y header select bit 0: no proprietary header exists on the front of i eee 802.3 frames. 1: four bytes of proprietary hea der information exist on the front of ieee 802. 3 frames. these bytes will be ignored by the crc function. bit 2: reserved. read = 0b; must write 0b. bit 1: lenchk: frame length checking enable bit 0: frame length checking is disabled. 1: transmit and receive frame lengths are compared to the length/type field. if the length/type field represents a length then the check is perfor med. mismatches are reported in the transmit/ receive status vectors. bit 0: flldplx: full-du plex mode enable bit 0: mac operates in half-duplex mode. 1: mac operates in full-duplex mode. table 21. pad operation padmd1[7] padmd0[6] paden[5] crcen[4] action x x 0 0 no padding added on transmitted packets, check crc x x 0 1 no padding added on transmitted packets, append crc 0 0 1 1 pad short frames to 60 bytes, append crc x 1 1 1 pad short frames to 64 bytes, append crc 1 0 1 1 auto detect tagged vlan frames (ieee802.1q) if untagged: pad to 60 bytes, append crc if tagged: pad to 64 bytes, append crc
cp2200/1 84 rev. 1.0 indirect register 3. ipgt: back-t o-back inter-packe t gap register indirect register 4. ipgr: non-back- to-back inter-pack et gap register bits 15?7:reserved. read = 000000000b; must write 000000000b. bits 6?0: ipgt: back-to-back inter-packet gap register sets the minimum delay between the end of any tr ansmitted packet and the start of a new packet. in full-duplex mode, the register value should be se t to the desired number of time units (each time unit is 0.46 s) minus 3. the recommended setting is 0x15 (21d), which yields 9.6 s. in half-duplex mode, the register value should be se t to the desired number of time units (each time unit is 0.46 s) minus 6. the recommended setting is 0x12 (18d), which yields 9.6 s. r/wr/wr/wr/wr/wr/wr/wr/w reserved bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 r/w r/w r/w r/w r/w r/w r/w r/w default value reserved ipgt 0x0000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 macaddr: 0x02 bit 15: reserved. read = 0b; must write 0b. bits 14?8:ipgr1: non-back-to-back inter-packet gap part 1 sets the optional carrier sense window referenced in i eee 802.3 section 4.2.3. 2.1. the range of values for this bit field are 0x00 to ipgr2. the recommended value is 0x0c. bit 7: reserved. read = 0b; must write 0b. bits 6?0: ipgr2: non-back-to-ba ck inter-packet gap part 2 sets the non-back-to-back inter-packet gap. the recommended value is 0x12, which represents a minimum inter-packet gap of 9.6 s. r/wr/wr/wr/wr/wr/wr/wr/w reserved ipgr1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 r/w r/w r/w r/w r/w r/w r/w r/w default value reserved ipgr2 0x0000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 macaddr: 0x03
cp2200/1 rev. 1.0 85 indirect register 5. cwmaxr: collision window and maxi mum retransmit register indirect register 6. maxlen: maximum frame length register note: this register does not require initialization an d will be left at its reset value by most systems. bits 15?14:reserved. read = 00b; must write 00b. bits 13?8:cw: collision window sets the collision window in which collisions occur in a properly configured network. the collision window is specified in the number of bytes from the start of transmission. the pream- ble and frame delimiter are included in the byte co unt. its default of 0x37 corresponds to the count of frame bytes at the end of the window. bits 7?4: reserved. read = 0 000b; must write 0000b. bits 3?0: maxr: maximum retransmit attempts sets the maximum number of retr ansmit attempts following a collis ion before aborting the packet due to excessive collisions. ieee 802.3 s pecifies a maximum va lue of 0x0f (15d). r/wr/wr/wr/wr/wr/wr/wr/w reserved cw bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 r/w r/w r/w r/w r/w r/w r/w r/w default value reserved maxr 0x370f bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 macaddr: 0x04 note: this register does not require in itialization and will be left at its re set value will be set to 1518 (0x05ee) by most systems. bits 15?0:maxf: maximum frame length specifies the maximum length of a receive frame. the default value is 0x600 (1536 octets). this register should be programmed if a shorter maximu m length restriction is desired. examples of shorter frame lengths are untagged (1518 octets) and tagged (1522 octets). if a proprietary header is allowed, this field shou ld be adjusted accordingly. r/wr/wr/wr/wr/wr/wr/wr/w bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 r/w r/w r/w r/w r/w r/w r/w r/w default value 0x0600 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 macaddr: 0x05
cp2200/1 86 rev. 1.0 indirect register 7. macad0: mac address 0 indirect register 8. macad1: mac address 1 bits 15?8:octet6: mac address, 6th octet this field holds the sixth (least si gnificant) octet of the mac address. bits 7?0: octet5: mac address, 5th octet this field holds the fifth octet of the mac address. r/wr/wr/wr/wr/wr/wr/wr/w octet6 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 r/w r/w r/w r/w r/w r/w r/w r/w default value octet5 0x0000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 macaddr: 0x10 bits 15?8:octet4: mac address, 4th octet this field holds the fourth octet of the mac address. bits 7?0: octet3: mac address, 3rd octet this field holds the third octet of the mac address. r/wr/wr/wr/wr/wr/wr/wr/w octet4 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 r/w r/w r/w r/w r/w r/w r/w r/w default value octet3 0x0000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 macaddr: 0x11
cp2200/1 rev. 1.0 87 indirect register 9. macad2: mac address 2 bits 15?8:octet2: mac address, 2nd octet this field holds the second octet of the mac address. bits 7?0: octet1: mac address, first octet this field holds the first (most significant) octet of the mac address. r/w r/w r/w r/w r/w r/w r/w r/w octet2 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 r/w r/w r/w r/w r/w r/w r/w r/w default value octet1 0x0000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 macaddr: 0x12
cp2200/1 88 rev. 1.0 15. physical layer (phy) the cp2200/1 has an ieee 80 2.3 compliant 10 base-t ethe rnet physical la yer transceiver that includes a receiver, transmitter, auto-negotiation, loopback, jabber, smart squelch, polarity co rrection, and link integrity functions. if enabled, the auto-negotiation function aut omatically negotiates the sp eed of the data link and the duplex mode. both half-duplex and full-duplex modes are supported. the physical layer is controlled and monitored through th ree registers: phycn, phyc f, and physta. the various functions and test modes that can be enabled and monito red through these registers are explained in the following sections. 15.1. auto-negotiati on and duplex mode auto-negotiation allows the cp220 0/1 to be connected to any 10/10 0/1000 base-t ethern et network and advertise its capabilities. auto-negotiation uses a series of fast lin k pulses to send 16-bit link code words. many conditions (e.g., failu re to detect fast link pulses) can cause auto-nego tiation to fail. on failure, the auto-negotiation failed interrupt will be generat ed, and/or the auto-negoti ation complete interrupt will not be ge nerated. the physta status register will indicate t he cause of failure, and the physical la yer will default to half-duplex mode. on success, the auto-negotia tion complete interrupt will be generated, an d the auto-neg otiation failed interrupt will not be generated. both interrupts must be checked to ensure that auto-negotiation has succeeded. the advertised link speed will always be 10base-t. the duplex mode (half or full) will be ne gotiated, and full duplex will be selected if supported by the network. full duplex mode allows t he physical layer to send and receive data at the same time. in half duplex mode, data can only be transmitted or received at any given time. full duplex mode provides overall higher performance and reduces collisions. software may also choose to advertise its ability to send and receive pause control packets by setting adpause (phycf.2) to ?1?. important note: when using auto-negotiation, the au to-negotiation enable bit autoneg (phycf.4) must be set to ?1? prior to enabling the physical layer. to restart auto-negotiation, the physical layer (transmitter, receiver, or both) must be disabled and reenabled. important note: the cp220x supports legacy link partners that ca nnot auto-negotiate. if the link partner cannot autonegotiate, then the physical la yer will default to half-duplex mode. 15.2. auto-negotiation synchronization the cp220x implements an autonegotiation scheme where autonegotiation is attempted for 250 ms, then a break- link delay of 1.5 seconds is inserted between auto-negot iation attempts. when the break-link delay is active, the cp220x does not listen for incoming auto-negotiation requests and does not attempt to auto-negotiate. if one device starts autonegotiation while the other device is in its ?break-link period?, the autonegotiation attempt will fail. if the devices are unsyncronized, this can lead to a situation where each device attempts to autonegotiate in the other device?s ?break-link period?. this can be solved by synchronizing one or both devices using the following procedure: step 1: disable the physical layer by writing 0x00 to the phycn register. step 2: enable the physical layer with link integrity test and auto-negotiation turned off. 1.disable the transmitter power save mode (t xpwr = 0x80) and set physical layer options (phycf = smsq | jabber | adpause | autopol). 2.enable the physical layer (phyen = 1). 3.wait for the physical layer to power up. see physical layer startup time in table 22 on page 93. 4.enable the transmitter and receiver (txen = 1 and rxen = 1). step 3: poll the wake-on-lan interrupt flag (w akeint) to detect if a lin k partner is present. 1.if there is a signal, wait 250 ms then begin autonegotiation. 2.if there is no signal, wait 1.5 seconds then begin autonegotiation.
cp2200/1 rev. 1.0 89 15.3. loopback mode loopback mode provides th e ability to transfer data from the physical layer?s output directly to it?s input to aid in system debugging. when phycn.3 is set to ?1?, transmit dat a is looped back to the receiver via an internal analog path. the transmit drivers and receive input circuitry ar e bypassed, isolating the device from the network. this prevents network traffic from affect ing the result of any system self-t ests and guarantees a collision-free environment. 15.4. link integrity function the link integrity fu nction provides the ability to detect and respond to a 10 base-t link failure. when such a failure is detected, the transmitter and receiver are automa tically disabled, and the state of the link is reported in linksta (phycn.0). the host can disable the link integrity function by clearing linkint (phycf.6) to ?0?. when the link integrity function is disabled, the physical laye r will operate regardless of the presence of link pulses. 15.5. receiver smart squelch a nd automatic polarity correction the physical layer receiver can detect and correct for noise or incorrect polarity of the received signal. if the receiver smart squelch feature is enab led by setting smsq (phycf.7) to ?1?, the receiver circuitry performs a combination of amp litude and timing measurements (in accordance with ieee 802.3) to determine the validity of received data. this prevents noise from falsely trig gering the receiver in the absence of valid data. automatic polarity correction can automat ically detect and correct the polarity of the received data to compensate for a wiring error at either end of the 10 base-t cable. wh en automatic polarity correcti on is enabled by setting autopol (phycf.1) to ?1?, the polarity of the receive data is indicated in polrev (phycn.1). when automatic polarity detection is disabled, the polarity of the receive data can be manually reversed by setting revpol (phycf.0) to ?1?. 15.6. transmitter jabber function provides the ability to au tomatically disable the transmitte r if software attemp ts to transmit a packet longer than the maximum allowed packet length (per ieee 802.3). the host processor will be notified via the jabber detected interrupt if a jabber condition is automatically han dled by the hardware. en abling the jabber function is recommended to ensure that the embedded system using the cp2200/1 for ethernet communication does not generate a jabber condition on the wire.
cp2200/1 90 rev. 1.0 15.7. initializing the physical layer the physical layer should be configured to the desired mode prior to setting the enable bit phyen (phycn.7). the following procedure should be used to initialize the physical layer: step 1: if auto-negotiation is used, implement the syn chronization procedure in section 15.2 on page 88. step 2: disable the physical layer by writing 0x00 to the phycn register. step 3: configure desired options using the phycn and phycf registers: 1.specify the duplex mode or enable auto-negotiation. 2.enable or disable loopback mode. 3.disable the transmitter power save mode (txpwr = 0x80). 4.enable the desired functions such as receiver smart squelch, auto matic polarity correction, link integrity, jabber protection, and pause packe t capability advertisement. 5.if automatic polarity correction is dis abled, manually set the desired polarity. step 4: enable the physical layer: 1.enable the physical layer (phyen = 1). 2.wait for the physical layer to power up. see physical layer startup time in table 22 on page 93. 3.enable the transmitter and receiver (txen = 1 and rxen = 1). step 5: wait for auto-negotiation to complete. if auto-ne gotiation is not enabled, software may wait for a valid link or go directly to mac initialization. step 6: enable the desired activity, link, or activi ty/link leds using the register 15, ?iopwr: port input/ output power register,? on page 45. step 7: initialize the mac to the same duplex mode r eported by the physical layer in the phycn register. note: step 6 and step 7 are repeated in the reset initialization pr ocedure. software only needs to perform these steps once.
cp2200/1 rev. 1.0 91 register 70. phycn: physical layer control register important note: when using auto-negotiation, the auto-negotiation enable bit, autoneg (phycf.4), must be set to ?1? prior to setting phyen, txen, and rxen to 1. to restart auto-negotiation, clear one of the three enable bits (phyen, txen , and rxen) to ?0? then set it back to ?1?. bit 7: phyen: physical layer enable 0: the physical layer is pl aced in a low-power state with limited functionality. 1: the physical layer is placed in a normal power state and is fully functional. bit 6: txen: transmitter enable 0: physical layer?s transmitter is placed in a low-power state. packet transmission and link pulse generation functions are disabled. 1. physical layer?s transmitter is enabled. bit 5: rxen: receiver enable 0: physical layer?s receiver is placed in a low-power state. packet reception is disabled. 1: physical layer?s re ceiver is enabled. bit 4: dplxmd: full-duplex mode enable bit note: this bit is read-only when auto-negotiation is enabled. 0: half-duplex mode is selected. 1: full-duplex mode is selected. bit 3: lbmd: loopback mode enable bit note: loopback mode is automatically disa bled if a jabber condition is detected. 0: loopback mode is disabled. 1: loopback mode is enabled. bit 2: lprfault: link partner remote fault (local fault) indicator 0: normal operation. 1: the link partner has detected a link fault and ha s sent notification during auto-negotiation. this condition can occur if the local transmitter is disabled and link pulses are no longer generated. bit 1: polrev: polarity reversed indicator 0: incorrect link polarity has not been detected. 1: incorrect link polarity de tected. link polarity has been automatically reversed. bit 0: linksta: link status indicator 0: link is bad. 1: link is good. r/w r/w r/w r/w or ro r/w r r r reset value phyen txen rxen dplxmd lbmd lprfault polrev linksta 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x78
cp2200/1 92 rev. 1.0 register 71. phycf: physical la yer configurat ion register bit 7: smsq: receiver smart squelch enable bit 0: receiver smart squelch is disabled. 1: receiver smart squelch is enabled. bit 6: linkint: link integrity function enable bit note: when enabled, the link integrit y function will automatically disa ble the transmitter and receiver and update linksta (phycn.0) if a link failure is detected. 0: link integrity function is disabled. 1. link integrity function is enabled. bit 5: jabber: jabber protecti on function enable bit note: when enabled, the jabber protection function will automatically disabl e loopback mode if a jabber condition is detected. 0: jabber protection function is disabled. 1: jabber protection function is enabled. bit 4: autoneg: auto-neg otiation enable bit 0: auto-negotiation function is disabled. 1: auto-negotiation function is enabled. bit 3: reserved. read = 0b; must write 0b. bit 2: adpause: advertise pause packet capability 0: indicates (during auto -negotiation) that the cp2200/01 does not have pause packet capability. 1: indicates (during au to-negotiation) t hat the cp2200/01 does have pause packet capability. bit 1: autopol: automatic pola rity correction enable bit 0: automatic receiver polari ty correction is disabled. 1: automatic receiver pola rity correction is enabled. bit 0: revpol: polarity reversal bit note: this bit is ignored if automa tic polarity correction is enabled. 0: the receiver polarity is normal. 1: the receiver polarity is reversed. r/w r/w r/w r/w r/w r/w r/w r/w reset value smsq linkintg jabber autoneg reserve d adpause autopol revpol 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x79
cp2200/1 rev. 1.0 93 register 72. physta: physic al layer status register table 22. 10base-t interface dc electrical characteristics v dd = 3.1 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units transmitter differential output voltage (peak) 2.2 2.5 2.8 v receiver normal squelch level (peak) ? 585 ? mv receiver low squelch level ? 330 ? mv physical layer startup time ? 1 ? ms note: the auto-negotiation stat es and error types are described in claus e 28 of ieee 802.3. bit 7: lgcilf: link good check incompatible link failure 0: normal operation. 1: auto-negotiation failed due to an incompatible link. bit 6: lgclsf: link good check line status failure 0: normal operation. 1. auto-negotiation failed due to a link fault. bit 5: akdlf: acknowledge detect link failure 0: normal operation. 1: auto-negotiation failed due to lack of reception of fast link pulses. bit 4: akdamf: acknowledge detect acknowledge match failure 0: normal operation. 1: auto-negotiation failed due to reception of a link code word with the ack bit cleared. bit 3: akdcmf: acknowledge dete ct consistency match failure 0: normal operation. 1: auto-negotiation failed due to reception of inconsistent link code words. bit 2: abdlf: ability detect link failure 0: normal operation. 1: auto-negotiation failed due to lack of reception of fast link pulses. bit 1: abdakmf: ability detect acknowledge match failure 0: normal operation. 1: auto-negotiation failed due to the recept ion of link code word(s) with the ack bit set. bit 0: abdabmf: ability dete ct ability match failure 0: normal operation. 1: auto-negotiation failed due to the lack of reception of three consecutive link code words. rrrrrr r rreset value lgcilf lgclsf akdlf akdamf akdcm f abdlf abdakmf abdabmf 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address: 0x80
cp2200/1 94 rev. 1.0 figure 19. 10base-t transmit figure 20. 10base-t receive table 23. 10base-t transmit switching characteristics v dd = 3.1 to 3.6 v, ?40 to +85 c unless otherwise specified. symbol parameters min typ max units t txjit tx pair jitter into 100 load ? 1 ? ns t txhld tx pair positive hold time at end of packet ? 200 ? ns t txret tx pair return to < 50 mv after last positive transition ?210?ns table 24. 10base-t receive switching characteristics v dd = 3.1 to 3.6 v, ?40 to +85 c unless otherwise specified. symbol description min typ max units t rxjit allowable received jitter ? ? 13.5 ns t csa carrier sense assertion delay ? 400 ? ns t ipb invalid preamble bits af ter assertion of carrier sense 2?2bits t csd carrier sense deassertion delay ? 200 ? ns tx t txjit ... 50mv t txret t txhld rx t rxjit ... t csd t csa t ipb ... carrier sense (internal)
cp2200/1 rev. 1.0 95 figure 21. 10base-t link integrity table 25. 10base-t link integrity switching characteristics v dd = 3.1 to 3.6 v, ?40 to +85 c unless otherwise specified. symbol description min typ max units t txlp1 first transmitted link pulse after last transmitted packet ?16?ms t txlp2 time between transmitted link pulses ? 16 ? ms t txlpw width of transmitted link pulses 80 100 210 ns t rxlp1 received link pulse separation 8 ? 24 ms t lpled last receive activity to link fail ? 150 ? ms rx t lpled link (led driver) ... ... ... t rxlp1 receive link integrity transmit link integrity tx ... ... ... t txlp1 t txlp2 t txlpw
cp2200/1 96 rev. 1.0 16. parallel interface the cp2200/1 has an 8-bit parallel host interface used to access the direct registers on the device. the parallel interface supports multiplexed or non- multiplexed operation using the intel ? or motorola ? bus format. the muxen pin can be driven high to place the device in multiple xed operation or driven low to select non-multiplexed operation. the moten pin can be driven high to place the device in motorola bus format or driven low to place the device in intel bus format. notes: 1. the CP2201 (28-pin package) can only be used in multiplexed mode. 2. the pcb traces connecting rd , wr , cs , ale, and all address and data lines should be matched such that the propagation delay does not vary by more than 5ns between any two signals. a parallel interface read or write operation typically re quires 260 ns (non-multiplexed) or 300 ns (multiplexed) to transfer one byte of data. if back-to-back operations are scheduled on a non-multiplexed bus, data rates up to 30 mbps can be achieved. tables 26 through 29 provi de detailed information about bus timing in each mode. 16.1. non-multiplexed intel format figure 22. nonmuxed intel read valid address t vd2 t hold t vd1 t as a[7:0] d[7:0] rd valid data t rd t ahr notes: 1. cs must be asserted with or before rd. 2. wr must remain de-asserted during a read. valid address t dh t hold t wr t as a[7:0] d[7:0] wr valid data t ahw t ds notes: 1. cs must be asserted with or before wr. 2. rd must remain de-asserted during a write.
cp2200/1 rev. 1.0 97 figure 23. nonmuxed intel write table 26. non-multiplexed intel mode ac parameters symbol description min typ max units t as address setup time (read/write) 30 ? ? ns t rd rd low pulse width (read) 160 ? ? ns t vd1 rd falling to valid data out (read) ? ? 140 ns t vd2 rd rising to data bus tri-state (read) ? 60 ? ns t wr wr low pulse width (write) 120 ? ? ns t ds data setup time (write) 40 ? ? ns t dh data hold time (write) 20 ? ? ns t ahr address hold time (read) 30 ? ? ns t ahw address hold time (write) 30 ? ? ns t hold hold delay (read/write) 60 ? ? ns
cp2200/1 98 rev. 1.0 16.2. multiplexed intel format figure 24. multiplexed intel read figure 25. multiplexed intel write t vd2 t hold t vd1 ad[7:0] ale rd t rd t ale1 t as t ah valid address t ale2 valid data notes: 1. cs must be asserted with or before rd. 2. wr must remain de-asserted during a read. t dh t hold t ds ad[7:0] ale wr t wr t ale1 t as t ah valid address t ale2 valid data notes: 1. cs must be asserted with or before wr 2. rd must remain de-asserted during a write.
cp2200/1 rev. 1.0 99 table 27. multiplexed intel mode ac parameters parameter description min typ max units t ale1 ale high pulse width 40 ? ? ns t ale2 ale falling to rd/wr falling 40 ? ? ns t as address setup time (read/write) 40 ? ? ns t ah address hold time (read/write) 40 ? ? ns t rd rd low pulse width 160 ? ? ns t vd1 rd falling to valid data out ? ? 140 ns t vd2 rd rising to data bus tri-state ? 60 ? ns t wr wr low pulse width 120 ? ? ns t ds data setup time (write) 40 ? ? ns t dh data hold time (write) 40 ? ? ns t hold hold delay (read/write) 60 ? ? ns
cp2200/1 100 rev. 1.0 16.3. non-multiplexed motorola format figure 26. nonmuxed motorola read figure 27. nonmuxed motorola write valid address t vd2 t hold t vd1 t as a[7:0] d[7:0] /ds valid data t dsr t ahr r/w t rws t rwh note: /cs must be asserted with or before /ds. valid address t hold t as a[7:0] d[7:0] /ds t dsw t ahw r/w t rws t rwh t dh valid data t ds note: /cs must be asserted with or before /ds.
cp2200/1 rev. 1.0 101 table 28. non-multiplexed motorola mode ac parameters parameter description min typ max units t as address setup time (read/write) 30 ? ? ns t rws r/w setup time (read/write) 30 ? ? ns t dsr ds low pulse width (read) 160 ? ? ns t vd1 ds falling to valid data out (read) ? ? 140 ns t vd2 ds rising to data bus tri-state (read) ? 60 ? ns t dsw ds low pulse width (write) 120 ? ? ns t ds data setup time (write) 40 ? ? ns t dh data hold time (write) 20 ? ? ns t ahr address hold time (read) 30 ? ? ns t ahw address hold time (write) 30 ? ? ns t rwh r/w hold time (read/write) 20 ? ? ns t hold hold delay (read/write) 60 ? ? ns
cp2200/1 102 rev. 1.0 16.4. multiplexed motorola format figure 28. multiplexed motorola read figure 29. multiplexed motorola write r/w t rws t rwh as t as1 t as2 t vd2 t vd1 ad[7:0] t as t ah valid address valid data t hold /ds t dsr note: /cs must be asserted with or before /ds. r/w t rws t rwh as t as1 t as2 ad[7:0] t as t ah valid address t hold /ds t dsw valid data t dh t ds note: /cs must be asserted with or before /ds.
cp2200/1 rev. 1.0 103 table 29. multiplexed motorola mode ac parameters parameter description min typ max units t as1 as high pulse width (read/write) 40 ? ? ns t as2 as falling to ds falling (read/write) 40 ? ? ns t as address setup time (read/write) 40 ? ? ns t ah address hold time (read/write) 40 ? ? ns t rws r/w setup time (read/write) 40 ? ? ns t dsr ds low pulse width (read) 160 ? ? ns t vd1 ds falling to valid data out (read) ? ? 140 ns t vd2 ds rising to data bus tri-state (read) ? 60 ? ns t dsr ds low pulse width (write) 120 ? ? ns t ds data setup time (write) 40 ? ? ns t dh data hold time (write) 60 ? ? ns t rwh r/w hold time (read/write) 60 ? ? ns t hold hold delay (read/write) 60 ? ? ns
cp2200/1 104 rev. 1.0 17. revision-specific behavior this chapter contains behavioral differences between cp 220x "rev c" and behavior as stated in the data sheet. 17.1. revision identification the lot id code on the top side of th e device package can be used for deco ding device revision information. on cp220x devices, the revision letter is the first letter of the lot id code. figures 30 and 31 show how to find the lot id code on the top side of the device package. figure 30. device package?tqfp 48 figure 31. device package?qfn 28 cp2200 c clz9l this first character identifies the silicon revision silabs CP2201 c cnzw2 this first character identifies the silicon revision
cp2200/1 rev. 1.0 105 17.2. mac address filtering problem for unicast packets received over the ethernet wire, the rece ive filter only validates the first 5 bytes of the 6-byte ethernet mac address. any packet addressed to a device whose mac address only differs in the 6th byte will be allowed to pass throu gh the receive filter. workaround the ethernet driver on the host controlle r should verify that the 6th byte of ea ch packet (i.e., the final byte of the mac address) matches its assigned mac address. if it detects a mismatch, the packet should be discarded by writing 1 to the rxskip bit. implications on throughput this behavior does not slow down the rate which the embedded system can send or receive packets, since the cp220x must receive and filter all packets on the network. however, it can interrupt the host controller for received packets addressed to another device with a similar mac address (where the only difference is in the 6th byte) on the same subnet. on a managed switch network, present on most corporate lans, the effect of this behavior is minimal due to the fact that the managed switch filters out unicast packets not addressed to the receiving ethernet device.
cp2200/1 106 rev. 1.0 d ocument c hange l ist revision 0.4 to revision 0.41 modified figure 2, ?typical connection diagram (non -multiplexed),? on page 6 and figure 3, ?typical connection diagram (multip lexed),? on page 7 for improved em i emmissions and common mode stability. revision 0.41 to revision 1.0 added maximum supply current spec ification in table 2 on page 9. updated the maximum xtal1 input low voltage specification from 0.8 to 0.7 v (see table 8 on page 20). updated the maximum rst input pullup current specification from 40 to 50 a (see table 13 on page 42). updated the non-multiplexed emif address hold time from 20 to 30 ns and the t vd2 specification from 40 to 60 ns. note that the t hold specification is unchanged from its value of 60 ns; therefore, changes to host timing will not be required in most applicat ions. see section 16 on page 96. added a revision-specific behavior chapter. see section 17 on page 104. removed text indicating that all packets on the wire can be received and buffered by the cp220x.
cp2200/1 rev. 1.0 107 n otes :
cp2200/1 108 rev. 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 email: mcuinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and usbxpre ss are trademarks of silicon laboratories inc. intel, motorola, and any other products or brandnames mentioned herein are trademarks or register ed trademarks of their respect ive holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsi bility for any consequences resu lting from the use of information included herein. additionally, silicon laborator ies assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no war- ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon labor atories assume any liability arising out of the application or use of any pr oduct or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages . silicon laboratories products are not de signed, intended, or authorized for use in appli- cations intended to support or sustain life, or for any other appl ication in which the failure of the silicon laboratories prod uct could create a situation where personal injury or death may occur. should bu yer purchase or use silicon laboratories products for any such u nintended or unauthorized application, buyer sha ll indemnify and hold silicon laboratories harmless against all claims and damages.

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